HeAP: Heterogeneous Analytical Placement for FPGAs

1. FPL 2012 Marcel Gort and Jason Anderson HeAP:Heterogeneous Analytical Placement for FPGAs

2. Motivation • CAD for FPGAs takes too long (up to a day). • FPGA placement contributes to a large proportion of overall CAD time. • In ASIC domain, where millions of cells are handled by placement, fast analytical methods dominate. • Recent work [1] adapted FastPlace to homogeneous FPGAs. • vs. VPR: ~13x speedup with 20% worse wirelength. • Can we use analytical methods to place cells onto a realistic heterogeneous FPGA? 1. Bian H., Ling A., Choong A., Zhu J. Towards scalable placement for FPGAs. in FPGA 2010

3. Analytical Placement (AP) • Objective function: Half-Perimeter Wirelength (HPWL) • Minimizing objective function: • Solve system of linear equations generated from connections between cells. • Convert multi-pin nets to 2-pin nets. • Create system of linear equations to solve weighted sum of squared distances between cells. • Solve system using off-the-shelf linear systems solver.

4. IO A B C IO 0 2 3 1 Φ = Min [ (XB – XA)2 + (XC – XB)2 + (XA – 0)2 + (3 – XC)2 ]

5. IO A B C IO 0 2 3 1 2 -1 0 -1 2 -1 0 -1 2 XA XB XC 0 0 3 X =

6. IO A B C IO 0 2 3 1 2 -1 0 -1 2 -1 0 -1 2 XA XB XC 0 0 3 X = XA = 0.75, XB=1.5, XC=2.25

7. IO A B C IO 0 2 3 1 2 -1 0 -1 2 -1 0 -1 2 XA XB XC 0 0 3 X = XA = 0.75, XB=1.5, XC=2.25

8. Actual Solved Solution Need to spread cells!

9. AP Overview Generate X and Ymatrices based on netlist Solve Perturb formulation based on spreading Spread cells to legalize solution Good enough? No Yes Refinement

10. Legalized Solution

11. Spreading • Adapted from SimPL [2]. • Find over-utilized area. 2. Myung-Chul K., Dong-Jin L., Markov I. SimPL: An Effective Placement Algorithm. in ICCAD 2010

12. Spreading • Adapted from SimPL [2]. • Find over-utilized area. • Find a larger surrounding area that can accommodate all cells within it.

13. Spreading • Adapted from SimPL [2]. • Find over-utilized area. • Find a larger surrounding area that can accommodate all cells within it. • Split the cells into two sets.

14. Spreading • Assign an area to each cell which is proportional to the total area of the cells.

15. Spreading • Assign an area to each cell which is proportional to the total area of the cells. • Spread each set of cells separately, within the area assigned to it.

16. Spreading • Assign an area to each cell which is proportional to the total area of the cells. • Spread each set of cells separately, within the area assigned to it. • Alternate x and y spreading directions until solution is legal.

17. Spreading • Assign an area to each cell which is proportional to the total area of the cells. • Spread each set of cells separately, within the area assigned to it. • Alternate x and y spreading directions until solution is legal.

18. Spreading • Assign an area to each cell which is proportional to the total area of the cells. • Spread each set of cells separately, within the area assigned to it. • Alternate x and y spreading directions until solution is legal.

25. AP Overview Generate X and Ymatrices based on netlist Solve Perturb formulation based on spreading Spread cells to legalize solution Good enough? No Yes Refinement

26. Pseudo-connections A IO IO Solved solution B C 0 2 3 1 A IO IO Legalized solution B C 0 2 3 1

27. Pseudo-connections A IO IO Solved solution B C 0 2 3 1 A IO IO Legalized solution B C 0 2 3 1

28. Pseudo-connections A IO IO Solved solution B C 0 2 3 1 Weighted pseudo-connections between cells and their legalized placements.

29. AP Overview Re-generate X and Ymatrices based on perturbed formulation Solve Perturb formulation based on spreading Spread cells to legalize solution Good enough? No Yes Refinement

30. HeAP • Analytical placement framework that targets commercial FPGAs. • Currently supports Cyclone II FPGAs. • Supports RAMs, DSPs, LABs, hard macros (carry chains). • Uses Quartus University Interface Program (QUIP) to replace the placer in Quartus II.

31. AP for FPGAs FPGA ASIC

32. AP for FPGAs FPGA ASIC

33. AP for FPGAs FPGA ASIC

34. AP for FPGAs • Snap to Grid – cut generation in spreading is multi-objective. FPGA ASIC

35. AP for FPGAs • Snap to Grid – cut generation in spreading is multi-objective. • Carry chains – relative cell placements must be maintained. FPGA ASIC

36. AP for FPGAs • Snap to Grid – cut generation in spreading is multi-objective. • Carry chains – relative cell placements must be maintained. • Cell type can only fit in correct slot type (e.g. RAMs in RAM slots). FPGA ASIC

37. AP for FPGAs – Spreading • Spread each cell type separately. • Maintain legality. FPGA

38. AP for FPGAs – Spreading • Spread each cell type separately. • Maintain legality.

39. AP for FPGAs – Spreading • Spread each cell type separately. • Maintain legality.

40. AP for FPGAs – Spreading • Spread each cell type separately. • Maintain legality.

41. AP for FPGAs – Spreading • Spread each cell type separately. • Maintain legality.

42. AP for FPGAs – Spreading • Spread each cell type separately. • Maintain legality.

43. AP for FPGAs – Spreading • Spread each cell type separately. • Handle legality in spreading.

44. AP for FPGAs – Solving • Solver doesn’t know about resource constraints but… • We can encourage solver to place a cell close to a legal slot by adding a pseudo-connection between that cell and the slot. • After enough iterations, solver will begin to generate solutions that are close to legal.

45. AP for FPGAs – Solving • Solver doesn’t know about resource constraints but… • We can encourage solver to place a cell close to a legal slot by adding a pseudo-connection between that cell and the slot. • After enough iterations, solver will begin to generate solutions that are close to legal.

46. AP for FPGAs – Solving • Solver doesn’t know about resource constraints but… • We can encourage solver to place a cell close to a legal slot by adding a pseudo-connection between that cell and the slot. • After enough iterations, solver will begin to generate solutions that are close to legal.

47. AP for FPGAs – Solving • Solver doesn’t know about resource constraints but… • We can encourage solver to place a cell close to a legal slot by adding a pseudo-connection between that cell and the slot. • After enough iterations, solver will begin to generate solutions that are close to legal. • Solve different types of cells together or separately?

48. Solving Orders All Initial Placement Solve all Spread DSPs Spread RAMs Spread LABs Solve all Spread DSPs Spread RAMs Spread LABs

49. Solving Orders All Rotate Initial Placement Initial Placement Solve all Solve DSPs Spread DSPs Spread DSPs Solve RAMs Spread RAMs Spread LABs Spread RAMs Solve LABs Solve all Spread DSPs Spread LABs Solve DSPs Spread RAMs Spread LABs Spread DSPs

50. Solving Orders All + Rotate Initial Placement Solve all Solve DSPs Spread DSPs Spread DSPs Solve RAMs Spread RAMs Spread LABs Spread RAMs Solve LABs Spread LABs Solve all