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CPU08 RESETS & INTERRUPTS

CPU08 RESETS & INTERRUPTS. CPU08 TOPICS. Resets & Interrupts Kinds Break Interrupt (see Break Module) Exception Reset processing Interrupt processing Vector Table. Resets & Interrupts. Resets initialize the CPU to a known state

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CPU08 RESETS & INTERRUPTS

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  1. CPU08RESETS&INTERRUPTS

  2. CPU08 TOPICS • Resets & Interrupts • Kinds • Break Interrupt (see Break Module) • Exception • Reset processing • Interrupt processing • Vector Table

  3. Resets & Interrupts • Resets initialize the CPU to a known state • All resets are managed through the System Integration Module • Reset types: • Power On – External Pin • COP – LVI • Illegal Address – Illegal Opcode • Interrupts suspend normal processing so the CPU can perform some requested service • Interrupt sources • IRQ1 – IRQ2 • SCI – SPI • TIM – DMA • CGM (PLL) – SWI

  4. Exception Processing Exception Processing Save Context (stacking) Application Program Exception Handler Find new Address (Vector Table) Load Address in PC EXCEPTION RTI Restore Old Context

  5. Exception Processing • Resets and Interrupts are both CPU exceptions (to normal processing) • Determining what type of handling is required, is called exception processing • Exception processing is handled through discrete tasks • Different for resets and interrupts • Recognition • Arbitration • Stacking • Vector fetching

  6. Exception Processing- Recognition- • Detection of either a Reset or a pending Interrupt • Resets: • Recognized and acted upon immediately once asserted • Interrupts: • Recognized during last cycle of current instruction • Unless asserted during last cycle • Will be recognized during last cycle of next instruction • Acted upon after last cycle of current instruction

  7. Exception Processing- Arbitration - • Resets: • Equal and highest priority • No arbitration • Interrupts: • Differing priorities • Lower than resets • Performed by SIM

  8. Lower Address Condition Code Register INTERRUPT RETURN Accumulator Index Register X Program Counter (H) Program Counter (L) Higher Address Exception Processing- Stacking - • Saving of CPU information • Resets: • No stacking performed • CPU state is reset • Interrupts: • Stacks CPU registers • PC, X, A, CCR • H register is not stacked • Compatibility

  9. Exception Processing- Vector Fetching - 68HC708XL36 Vector Table $FFE0 - $FFE1 IRQ2/Keypad • Resets: • All use same vector • Can determine source by examining a SIM register • Interrupts: • Vector depends on interrupt source $FFE2 - $FFE3 SCI Transmit $FFE4 - $FFE5 SCI Receive $FFE6 - $FFE7 SCI Error $FFE8 - $FFE9 SPI Transmit $FFEA - $FFEB SPI Receive $FFEC - $FFED TIM Overflow $FFEE - $FFEF TIM Channel 3 $FFF0 - $FFF1 TIM Channel 2 $FFF2 - $FFF3 TIM Channel 1 $FFF4 - $FFF5 TIM Channel 0 $FFF6 - $FFF7 DMA $FFF8 - $FFF9 PLL $FFFA - $FFFB IRQ1 $FFFC - $FFFD SWI $FFFE - $FFFF RESET

  10. RESET Set I-bit in CCR to prevent interrupts Reset internal registers. Includes CPU and sub module registers. See individual registers for reset states. Load Stack Pointer with $00FF User Monitor Mode ? Fetch Reset Vector Fetch Reset Vector from $FFFE-$FFFF from $FEFE-$FEFF Load Program Counter with contents of Reset Vector Begin execution Reset Processing

  11. INTERRUPT 1 Complete next instruction fetch Last cycle of current instruction (Unused) Complete next instruction fetch Unstack Condition Code register (Redundant) Unstack Accumulator Stack Program Counter Unstack X Index register Stack X Index register Unstack Program Counter Stack Accumulator Fetch next instruction Stack Condition Code register Set I bit to prevent interrupts Yes Interrupt Fetch vector 1 Pending? Load Program Counter with vector contents No First cycle of next instruction Begin execution. Service the interrupt. Interrupt Processing • Note that the H Index register is not saved on the stack. • The I-bit is cleared by the unstacking of the Condition Code Register.

  12. Masking • Enabling/Disabling of exception processing. • Resets: • Can NOT be masked. • Interrupts: • Can be masked • I bit enables/disables all interrupt processing • Local masks in peripherals for masking individual interrupts

  13. DESIGN EXERCISE PART2 • Write a code sequence • Executes at RESET • Calls your RAM initialization • How do you make sure this code executes at RESET? • Given: ORG $6E00STARTUP . . . . . . ; Program startup and initialization ORG $FFE0 ; Vector Table FCB IRQ2SRV ; IRQ2 Service Routine FCB SCIXMIT ; SCI Transmit Service Routine FCB SCIRECV ; SCI Receive Service Routine • • • FCB ????? ;Reset Handler

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