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COMBINATIONAL LOGIC

COMBINATIONAL LOGIC. Overview. Combinational vs. Sequential Logic. At every point in time (except during the switching. transients) each gate output is connected to either. V. or. V. via a low-resistive path. DD. ss. The outputs of the gates assume at all times the value.

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COMBINATIONAL LOGIC

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  1. COMBINATIONAL LOGIC

  2. Overview

  3. Combinational vs. Sequential Logic

  4. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit

  5. Static CMOS

  6. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high

  7. PMOS Transistors in Series/Parallel Connection

  8. Complementary CMOS Logic Style Construction (cont.)

  9. Example Gate: NAND

  10. Example Gate: NOR

  11. Example Gate: COMPLEX CMOS GATE

  12. 4-input NAND Gate Vdd Out GND In1 In2 In3 In4

  13. Standard Cell Layout Methodology

  14. Two Versions of (a+b).c

  15. Logic Graph

  16. Consistent Euler Path

  17. Example: x = ab+cd

  18. Properties of Complementary CMOS Gates

  19. Properties of Complementary CMOS Gates

  20. Transistor Sizing

  21. Propagation Delay Analysis - The Switch Model

  22. What is the Value of Ron?

  23. Numerical Examples of Resistances for 1.2mmCMOS

  24. Analysis of Propagation Delay

  25. Design for Worst Case

  26. Influence of Fan-In and Fan-Out on Delay

  27. tp as a function of Fan-In

  28. Fast Complex Gate - Design Techniques

  29. Fast Complex Gate - Design Techniques (2)

  30. Fast Complex Gate - Design Techniques (3)

  31. Fast Complex Gate - Design Techniques (4)

  32. Example: Full Adder

  33. A Revised Adder Circuit

  34. Ratioed Logic

  35. Ratioed Logic

  36. Active Loads

  37. Load Lines of Ratioed Gates

  38. Pseudo-NMOS

  39. Pseudo-NMOS NAND Gate VDD GND

  40. Improved Loads

  41. Improved Loads (2)

  42. Example

  43. Pass-Transistor Logic

  44. NMOS-only switch

  45. Solution 1: Transmission Gate

  46. Resistance of Transmission Gate

  47. S S Pass-Transistor Based Multiplexer S VDD GND In1 In2 S

  48. Transmission Gate XOR

  49. Delay in Transmission Gate Networks

  50. Elmore Delay (Chapter 8)

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