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SWITCH -MODE POWER SUPPLIES AND SYSTEMS

SWITCH -MODE POWER SUPPLIES AND SYSTEMS. Lecture No 7. Silesian University of Technology Faculty of Automatic Control, Electronics and Computer Sciences Ryszard Siurek Ph.D., El. Eng. Flyback converter. D 1. I p. I D. I 0. I C. C. R 0. U IN. Z p. Z S. U 0. I T. C IN. T. t.

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SWITCH -MODE POWER SUPPLIES AND SYSTEMS

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  1. SWITCH-MODE POWER SUPPLIES AND SYSTEMS Lecture No 7 Silesian University of Technology Faculty of Automatic Control, Electronics and Computer Sciences Ryszard Siurek Ph.D., El. Eng.

  2. Flyback converter D1 Ip ID I0 IC C R0 UIN Zp ZS U0 IT CIN T t T transfer ratio • exceptional topology comprising transformer and output choke in one magnetic • component • topology with lowest compenet count – cheapest solution L T IT ID D1 I0 IC C R0 UIN Zp ZS U0 CIN t T Compare to flyback switching regulator

  3. Flyback converter basic relations analysis Cycle I - transistor T is ON IT I0 D1 Ipmax IC UIN R0 C Zp ZS U0 B t IT BS T Magnetic energy stored in the core By the end of cycle I H Cycle II - transistor T is OFF ID ID D1 I0 IDmax IC dUp T R0 C Zp ZS t t’ B UIN nU0 U0 BS IT=0 T H Magnetic energy recovered from the core by the end of cycle II

  4. From energy balance : IDmax I0 (1) iD(t) ~ UC LS Ro (2) U0 From equation (1) : Al - core constant hence: U0 may be calculated also from energy balance: valid only in case of discontinuous flux (current) flow, it means t’ < T - t (3) At the point of t’ - ID(t’) = 0, hence: (4)

  5. From equation (4) : ID IDmax U0(R0) U’0(R’0 < R0) t t’ T Compare to flyback regulator for R0 < R0cr (I0 > I0cr) the flux in the core does not decay to 0 – so called „continuous flux flow” starts U0 IT g > 0,5 ITmax g =0,5 t T g < 0,5 ID IDmax = nITmax IDmax IDmin = nITmin I0kr I0 IDmin

  6. Real diagrams of flyback converters recovery of energy stored in the leakage inductance Dd Zp=Za D C R0 Zp ZS U0 CIN Za UIN Cs snubbar circuit for dumping overvoltage spikes and reducing transistor power losses T Rs Ds Advantages: Energy stored in leakage inductace is recovered, transitor voltage does not exceed 2UIN Disadvatages: Complicated and expensive transformer

  7. Leakage inductance measurement method LL LL D LL Rs Cs C R0 Zp ZS U0 Up UIN CIN T UT=Up+UIN Disadvatages: Energy stored in the leakage inductance is dissipated in resistor Rs, lower efficiency, necessity of power resistor utilisation, component heating, possibility of transitor voltage higher than 2UIN Advantages: Cheaper transformer, lack of extra overvoltage spikes due to residual leakage inductance This topology often used in low power converters up to 100W

  8. Multi - output coverters Flyback topology D1 ID1 I01 R01 US1 C1 ZS1 U01 D2 ID2 I02 Zp UIN T CIN R02 US2 C2 ZS2 U02 Feedback loop In II cycle U01 = US1 U02 = US2 In this topology output voltages are dependent only on the secondary numbers of turns. In case of perfect magnetic coupling only one output voltage may be regulated to obtain the regulation of other outputs. Valid for discontinuous as well as continuous current flow One of the cheapest and simple solution delivering several regulated output voltages.

  9. Forward converter D1 L1 Da D2 C R01 ZS1 U01 Zp CIN D3 L2 Za UIN D4 C R02 ZS2 U02 T This relation only valid in case of cotinuous magnetic flux (current) flow in L1 & L2

  10. Coupled output inductors D1 L1 Dd R01 D2 C1 ZS1 U01 Zp CIN D3 L2 Za UIN R02 D4 C2 ZS2 U02 T Equivalent output circuit valid for cycle I : L1 U01 L2 U02

  11. Equivalent output circuit valid for cycle II: L1 U01 L2 U02 To achieve proper relation between output voltages the following condition must be satisfied : • In real circuit: • diode voltage drop and nonlinear diode characteristics have significant influence on output voltages • influece of winding resistances • significant influence of leakage (poor winding coupling) Detailed relations of turns number for particular windings are usually set by the way of experiment in practice – equations presented above give only the rough approximation.

  12. The other way of obtaining auxilliary regulated output voltages with low load requirements : D2 C2 R2 U2 Da L2 D2 Zp=Za L D1 C R0 U0 Zp Zw CIN Zd UIN T C2 R2 U2 C2 R2 U2 z2 L2 L2 zL U0 L U0 L

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