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Introduction

Electronics for FTOF prototype: preliminary results of the 16- ch WaveCatcher board D.Breton & J.Maalmi (LAL Orsay).

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Introduction

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  1. Electronics for FTOF prototype:preliminaryresults of the 16-ch WaveCatcher boardD.Breton & J.Maalmi (LAL Orsay)

  2. For the test of the first prototype of the FTOF based on a two-bar setup on SLAC CRT, webuilt a synchronoussixteenchannelacquisition system based on 8 two-channel WaveCatcher V5 boards + a controllerboard. In order to increase the channeldensity and optimize the system, wedesigned a 16-channelboardbased on four 4-channel Front End Blocks will arrive nextweek! Said 4-channel front End Block was first implemented as a mezzanine compatible withCAEN Desktop Digitizerand VMEboards (up to 16 channels)  thisallowed us to perform first preliminarymeasurements, including time jitterbetween pulses. We are alsodesigning a 64-channel system based on four 16-channelboardssynchronized by a controllerboard. An up to 320-channel system isalsounder design. Introduction

  3. From the 16-chcrate to a 16-ch WaveCatcher 233 mm 8 x 75 = 600 mm ! 220 mm 145 mm

  4. Building large scalesystems Crate backplane interconnections Individual triggers Clock & common trigger DAQ connected to all boards or only to controller USB/ Ethernet • To synchronise N boards a controllerboardisneeded + backplane for the interconnections • we are building a very compact 64-channel system : •  canbeused for the FTOF sector prototype withfourteen 4-channel MCP-PMTs (SL10) • we are also building a 320-channel system in 6U-crate (SuperNemoexperiment). Controller board Up to 10 WaveCatcher boards Up to 10 WaveCatcher boards

  5. Block diagram of the 16-channel WaveCatcher • - This boardis compatible withbothSAM (256 cells/ch) and SAMLONG (1024 cells/ch) ASICs • (circularanalogmemories) • - SAMLONG: baseline. • - The boardcanbeconnected to a backplane => possibility to scale the system up to 320 channelsin a crate • - The first prototype willbeavailableverysoon (nextweek!!) SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC 4 Analog Input Trigger In/out FPGA SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC FPGA • 6U x 220mm Format • USB 480 Mbits/s • Optical fiberconnector SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC 4 Analog Input Trigger In/out FPGA SAMLONG Chip 1024 pts - 3.2 GS/s 2 Channels Dual 12 bits ADC

  6. 2-channel front-end diagram BACKPLANE Ch0 + Low Threshold - + High Threshold - Ch1 + ½ Front End FPGA (TimeStamp,Q,A) Low Threshold Trigger in - FPGA Controller + High Threshold - Trigger out Run, read Event data Ch0 SAMLONG (1024 samplingcells) clk 12-bit ADC Ch1 USB x 8

  7. Final • PCB design • (by P.Rusquart, LAL) • 1.6mm thick • 10 layers • 233 x 220 mm² • 3200 components • 25 power supplies (5 global, 20 local) • 4-channel blocks used as mezzanine on other boards

  8. Status leds 16 signal inputs (MCX connectors) Optical SFP connector Front USB connector

  9. 4-channel block Differential amplifiers 12-bit ADCs SAMLONG Asics Trigger discriminators Front-end FPGA Local supply regulators Calibration EEPROM (1Mbit) Offset and threshold DACs and buffers Input connectors

  10. Clock PLL distributor Middle right Fibre channel/ Conet SERDES Backplane parallel bus buffers Backplane 18-bit SERDES Controller FPGA SAMLONG + ADC for sampling digital signals Backplane connector

  11. DC/DC converters for digital supplies (3.3V, 2.5V, 1.2V) Top right VME connector (+5V supply only) Optional -5V DC/DC converter Oscillators for Serial Lite/ Fibre channel/ Conet User EEPROM (1Mbit) +5V supply bornier

  12. Bottom right Back USB connector FPGA configuration memory Clk input USB interface (FT2232H) Sync input Trig input Local supply regulators Trig output

  13. Present and future board features (not exhaustive) Possibility to add anindividual DC offset on each signal Possibility to chainchannels by groups of 2 2 individualtrigger discriminatorson eachchannel External and internal trigger + numerous modes oftriggering on coïncidence (11 possibilitiesincludingtwo pulses on the samechannel => useful for afterpulsestudies Embedded digital CFD for time measurement Embedded signal amplitude extraction Embedded charge mode (integrationstarts on threshold or at a fixed location) => high rates (~ 3.5 kEvents/s) 2 extra memorychannelsfor digital signals One pulse generatoron each input Externalclockinput for multi-board applications Embedded USB and Serial Lite/Fibre Channel/Conet interfaces Possibility to program the FPGAs via USB/Backplane/AlteraBlaster

  14. Front-end block has been integrated in a mezzanine The latter has been mounted on a CAEN USB-drivenmotherboard Almostfullyvalidated! First characterizationresults are available: noise level : 0.72 mV, signal bandwidth ~ 500 MHz (equivalent to single WaveCatcher board) This mezzanine permitted an anticipated hardware debug and predesign of firmware for the 16-channelboard (shouldbesold by CAEN soon).

  15. Acquisition Software: up to 16 ch soon 64 ch!

  16. Measurement panel

  17. Preliminaryresults • We send pulses from a pulse generator (1V pp, rise & fall time: 1.6 ns, FWHM 2 ns) • We vary the distance. Time jitterbetweentwochannels on the same SAMLONG chip: Δt ~ 0 ns (Ch1 – Ch0) jitter = 8.2 ps RMS Δt ~ 10 ns (Ch1 – Ch0) jitter = 10.7 ps RMS

  18. First Preliminaryresults Time jitterbetweentwochannels on different SAMLONG chips and on the same mezzanine: Δt ~ 0 ns (Ch2 - Ch0) jitter = 8.7 ps RMS Δt ~ 0 ns (Ch3- Ch0) jitter = 10 ps RMS Δt ~ 10 ns (Ch3- Ch0) jitter = 12.3 ps RMS

  19. First Preliminaryresults Time jitterbetweentwochannels on different SAMLONG chips and on the same mezzanine: Δt ~ 0 ns (Ch2 - Ch0) jitter = 8.7 ps RMS Δt ~ 0 ns (Ch3- Ch0) jitter = 10 ps RMS Δt ~ 10 ns (Ch3- Ch0) jitter = 12.3 ps RMS Δt ~ 20 ns (Ch2- Ch0) jitter = 12.6 ps RMS

  20. First Preliminaryresults Time jitterbetweentwochannels on different mezzanines: Δt ~ 7.5 ns (Ch4 - Ch0) jitter = 11.7 ps RMS Δt ~ 9 ns (Ch6- Ch0) jitter = 14.4 ps RMS Δt ~ 10 ns (Ch4- Ch0) jitter = 12.4 ps RMS Δt ~ 5 ns (Ch4- Ch0) jitter = 11.4 ps RMS

  21. Conclusion • We concentrated the WaveCatcher crate into a 16-channel board => This board can be plugged into a 6U VME crate to get the power • 4-channel front-end blocks have been validated on a mezzanine => Compatible with CAEN digitizer family • First results look good: time precision is equivalent to that of the crate • < 10ps rmsper channel even between different mezzanines • We are currently designing a compact 64-channel system • 25 cm x 10 cm x 30 cm with embedded power supply • Single link to the PC (USB or Ethernet) • Up to 320 channels can be housed inside a 6U crate => Such a system is currently being developped.

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