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BeamCal Front-End Design: Challenges, solutions and techniques

BeamCal Front-End Design: Challenges, solutions and techniques. Angel Abusleme, Angelo Dragone and Gunther Haller. Presentation Outline. BeamCal FE design challenges Solutions Techniques. BeamCal FE Design Challenges. High occupancy. High rate (3.25 MHz)

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BeamCal Front-End Design: Challenges, solutions and techniques

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  1. BeamCal Front-End Design:Challenges, solutionsand techniques Angel Abusleme, Angelo Dragone and Gunther Haller FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  2. Presentation Outline • BeamCal FE design challenges • Solutions • Techniques FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  3. BeamCal FE Design Challenges FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  4. High occupancy • High rate (3.25 MHz) • Peaking time limited to time between pulses (308ns) • Large memory required FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  5. Large input capacitance • Detector+wiring (CD): ~40pF • Implies increased voltage noise component FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  6. Large input signals • Large feedback capacitance (40pF) • Large charge amplifier output current to provide sufficient slew rate • Ballistic Deficit • Nonlinearity FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  7. Wide range of operation • 50x gain between science and calibration • Single circuit must cope with two different sets of specs • Challenges in calibration mode • Noise (still 40pF input capacitance) • Amplifier linearity is an issue FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  8. More BeamCal FE Challenges • Fast feedback requirement • Additional output • Low latency ADC • Radiation tolerance • Using non-standard transistor geometries • No models readily available • Low power dissipation • About 2mW per channel FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  9. Solutions FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  10. Gated front-end • This addresses high occupancy and limited peaking time • Charge amplifier and filter have periodic reset • This allows longer integration time, no tail • Time-domain noise analysis is required FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  11. This addresses slew rate problem Load branch borrows current from input device during settling Still nonlinearity and ballistic deficit are important issues Both are a consequence of pulse shaping Amplifier topology FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  12. Reconfigurable architecture • But “no shaper” implies “no problem” • Shaper will only be used in calibration FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  13. Digital memory • This addresses large storage requirement • Advantages of digital memory in 0.18um • More versatile solutions against SEE (e.g., parity) • No leakage • High density in 0.18-um technology FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  14. Dual feedback capacitance • This addresses dual range problem • New issues: additional noise and amplifier open-loop gain requirement • Gain and noise problems are mitigated by amplifier precharge… FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  15. Amplifier precharge idea • Improves linearity and SNR h FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  16. Amplifier precharge implementation FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  17. More solutions • Analog fast feedback • Still a low latency ADC is required • Radiation tolerance • TSMC 0.18 is inherently tolerant • Prototype with standard transistors will help to assess tolerance • Power dissipation • Analog front-end turned off between pulse trains • PSRR could become an issue… More on this in next part FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  18. Techniques FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  19. Differential circuits • Commonly used in precision, low voltage integrated circuits • Improved output swing, SNR and PSRR, reduced parasitics effects, but requires more power • This technique can help significantly to reduce the transient effects of switching the front-end power supply FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  20. Differential circuit implementation • Signal is pseudo differential at the charge amplifier, and fully differential at the filter FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  21. Switched-Capacitor filter • A SC filter is a sampled-data, analog filter • Widely used technique for IC filters since the 80’s • Resistors are simulated using capacitors and switches • Filter time constants are accurately set by capacitor ratios and external clock FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  22. More on SC filters • Operational transconductance amplifiers (OTA) are used instead of operational amplifiers • Ideally a voltage-controlled current source • No need for an output buffer, load is a capacitor • Settling time matters; settling transient doesn’t FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  23. Noise analysis based on gm/ID • MOSFET long channel models are not accurate for current technologies • Higher electric field • Moderate and weak inversion operation • SPICE models have hundreds of parameters • Great for simulation, bad for design purposes • gm/ID methodology overcomes this limitation • SPICE computes curves adequate for design FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  24. Example of gm/ID curves FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  25. gm/ID and noise analysis • Noise equations are not functions of gm/ID or any corresponding ratio… • But a simple normalization allows to have transistor noise equations as functions of gm/ID or corresponding ratios • SPICE computes noise curves, which are then available for precise noise calculations • Results are valid for any region of operation • Details to be shown in a future publication FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  26. Example of normalized noise curves FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  27. Tentative design schedule • April 2007: High level design complete • July 2007: Charge amplifier designed • May 2008: Filter designed • August 2008: ADC designed • September 2008: Memory designed • October 2008: Fast feedback designed • November 2008: Bias and supporting circuits • January 2009: Circuit layout complete • February 2009: Verification complete • April 2009: Prototype ready • June 2009: Prototype tests complete FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

  28. People • Angel Abusleme (PhD student)2 • Professor Martin Breidenbach1 • Angelo Dragone1 • Dietrich Freytag1 • Gunther Haller1 • Professor Bruce Wooley2 Affiliations • SLAC • Department of Electrical Engineering, Stanford University FCAL collaboration meeting, May 6-7, 2008, Krakow, Poland

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