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Power and Frequency Analysis for Data and Control Independence in Embedded Processors

Power and Frequency Analysis for Data and Control Independence in Embedded Processors. Farzad Samie Amirali Baniasadi Sharif University of Technology University of Victoria. This Work. Goal

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Power and Frequency Analysis for Data and Control Independence in Embedded Processors

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  1. Power and Frequency Analysis for Data and Control Independence in Embedded Processors Farzad Samie Amirali Baniasadi Sharif University of TechnologyUniversity of Victoria

  2. This Work Goal Power and frequency analysis for control independent and data independent instructions in embedded processors Motivation Embedded processors are becoming complex Modern embedded processors use speculation Mis-speculation causes performance and power penalty Power is a major concern in embedded processors Save power and gain performance

  3. This Work (cont.) Our Approach • Reducing wasted energy and time in mispredictions. How? • Identify and bypass Control Independent (CI) and Data Independent (DI) instructions. • CIs: Instruction executing independent of branch outcome. • CI-DI: CI Instructions executing with the same operands. Key Result: • 12% processor energy reduction.

  4. Background Branch Predictor Branch History Predicted direction Program Counter Predicted target address BranchPrediction

  5. Background (cont.) I1 I2 I3 Branch Inst. Not taken Taken I4 I10 Wrong Path (squashed) ? ? I5 I11 Right Path I6 I12 Misprediction Detection I7 I7 I8 I8 Control Independent Instructions (CIs) I9 I9

  6. Background (cont.) R1←R1+R2 R4←R1 If (R4=0) Not taken Taken R5←R4+1 R5←R4+1 R2←R4-R1 R3←0 R5←R2-R3 R5←R2-R3 R1←R1-1 R1←R1-1 R3←0 R4←R6+R4 Data Independent (CI-DI) R1←R4+R1 Data Dependent (CI-DD) R5←R5-2 Data Dependent (CI-DD) R3←R3-R4 Data Independent (CI-DI)

  7. CI-DI vs. CI-DD CI-DD Fetch Issue Dispatch Execute Write Back CI-DI • Bypassing CI-DIs saves more energy • No need to read operands/execute again • Bypassing CI-DIs provides higher performance • Not need to waste time for reading operand/executing

  8. Methodology • Modified SimpleScalar • Wattch for power measurement • MiBench: Embedded Benchmark Suite

  9. Distribution Wrong Path: 12%, CI: 5%, CI-DI: 2%

  10. CI Power Reduction in Different Units Max: branch predictor unit, Min: instruction cache

  11. CI Power Reduction in Stages Rijndael: low misprediction  low wrong path  low CIs

  12. Power Sensitivity to RUU size CI CI-DI Higher power dissipation for bigger RUU sizes

  13. Power Sensitivity to Execution Bandwidth CI CI-DI Higher power dissipation for wider execution bandwidth

  14. Power Sensitivity to Branch Predictor Size Little sensitivity to branch predictor size

  15. Related Work Rotenberg et. al: studied control independence in superscalar processors, HPCA99. Collins et. al: suggested mechanism to predict re-convergent point, Micro04. Lam and Wilson: studied impact of CIs on instruction level parallelism, ISCA92. Gandhi et. al: recover selected branch mis-prediction, HPCA04.

  16. Conclusion Categorize CI to CI-DI and CI-DD Potential power saving for bypassing CI and CI-DI instructions up-to 12% High sensitivity to RUU size High sensitivity to execution bandwidth Little sensitivity to branch predictor size

  17. Question ? Thank you

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