1 / 34

Cache memory

Cache memory. Prof. Sin-Min Lee Department of Computer Science. CS147 Lecture 16. Problem. Implement the following state diagram using T Flip-Flop(s) and J-K Flip-Flop(s). Number Of Flip-Flops Needed. Need 2 Flip-Flops 1 T Flip-Flop 2 JK Flip-Flop. Steps To Solve The Problem.

ezra-pace
Télécharger la présentation

Cache memory

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Cache memory Prof. Sin-Min Lee Department of Computer Science CS147 Lecture 16

  2. Problem Implement the following state diagram using T Flip-Flop(s) and J-K Flip-Flop(s)

  3. Number Of Flip-Flops Needed • Need 2 Flip-Flops • 1 T Flip-Flop • 2 JK Flip-Flop

  4. Steps To Solve The Problem Step 1 – Create state table Step 2 – K-Maps for QA+ and QB+ Step 3 – K-Maps for T and JK Flip-Flops Step 4 – Draw Flip-Flop diagram

  5. State Table Derived directly from the state diagram:

  6. K-Maps for QA+ and QB+ QA+ QB+

  7. JK Truth Table Let’s revisit JK Flip-Flops:

  8. T Truth Table Let’s revisit T Flip-Flops:

  9. K-Map for T T = QA’QB

  10. K-Map for J and K J K J = XQA’+ X’ QA K = X

  11. Draw Flip-Flop Diagram

  12. Two Basic Types of Memory • RAM (Random Access Memory) • Used to store programs and data that computer needs when executing programs • Volatile and loses information once power is turned off

  13. 2 Basic Types of Memory • ROM (Read-Only Memory) • Stores critical information necessary to operate the system, such as program necessary to boot computer • Not volatile and always retains its data • Also embedded in systems where programming does not need to change

  14. Memory Hierarchy • Hierarchal Memory • Approach in which computer systems use combination of memory types to provide best performance at best cost • Basic types that constitute hierarchal memory system include registers, cache, main memory and secondary memory

  15. Memory Hierarchy • Today’s computers each have small amount of very high-speed memory, called cache where data from frequently used memory locations may be temporarily stored • Cache is connected to main memory, which is typically medium-speed memory • Main memory is complemented by secondary memory, composed of hard disk and various removable media

  16. The Memory Hierarchy

  17. Cache Memory • Physical memory is slow (more than 30 times slower than processor) • Cache memory uses SRAM chips. • Much faster • Much expensive • Situated closest to the processor • Can be arranged hierarchically • L1 cache is incorporated into processor • L2 cache is outside

  18. Cache Memory- Three LevelsArchitecture Memory Multi- Gigabytes Large and Slow 160 X Cache Control Logic 2 Gigahertz Clock 8X 2X 16X L3 Cache Memory L2 Cache Memory L1 Cache Memory 32 Kilobytes 128 Kilobytes 16 Megabytes Featuring Really Non-Deterministic Execution Address Pointer

  19. Cache (2) • Every address reference goes first to the cache; • if the desired address is not here, then we have a cache miss; • The contents are fetched from main memory into the indicated CPU register and the content is also saved into the cache memory • If the desired data is in the cache, then we have a cache hit • The desired data is brought from the cache, at very high speed (low access time) • Most software exhibits temporal locality of access, meaning that it is likely that same address will be used again soon, and if so, the address will be found in the cache • Transfers between main memory and cache occur at granularity of cache lines or cache blocks, around 32 or 64 bytes (rather than bytes or processor words). Burst transfers of this kind receive hardware support and exploit spatial locality of access to the cache (future access are often to address near to the previous one)

  20. Where can a block be placed in Cache? (1) • Our cache has eight block frames and the main memory has 32 blocks

  21. Current CPUs

  22. Cache Performance • Cache hits and cache misses. • Hit ratio is the percentage of memory accesses that are served from the cache • Average memory access time TM = h TC + (1- h)TP Tc = 10 ns Tp = 60 ns

  23. Associative Cache FIFO h = 0.389 TM = 40.56 ns • Access order A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 V0 G3 C2 H7 I6 A0 B0 Tc = 10 ns Tp = 60 ns

  24. Direct-Mapped Cache h = 0.167 TM = 50.67 ns • Access order A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 V0 G3 C2 H7 I6 A0 B0 Tc = 10 ns Tp = 60 ns

  25. 2-Way Set Associative Cache LRU h = 0.31389 TM = 40.56 ns • Access order A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 V0 G3 C2 H7 I6 A0 B0 Tc = 10 ns Tp = 60 ns

  26. Associative Cache(FIFO Replacement Policy) A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0 G3 C2 H7 I6 A0 B0 Hit ratio = 7/18

  27. Two-way set associative cache(LRU Replacement Policy) A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0 G3 C2 H7 I6 A0 B0 Hit ratio = 7/18

  28. Associative Cache with 2 byte line size (FIFO Replacement Policy) A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0 G3 C2 H7 I6 A0 B0 A and J; B and D; C and G; E and F; and I and H Hit ratio = 11/18

  29. Direct-mapped Cachewith line size of 2 bytes A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0 G3 C2 H7 I6 A0 B0 A and J; B and D; C and G; E and F; and I and H Hit ratio 7/18

  30. Two-way set Associative Cachewith line size of 2 bytes A0 B0 C2 A0 D1 B0 E4 F5 A0 C2 D1 B0 G3 C2 H7 I6 A0 B0 A and J; B and D; C and G; E and F; and I and H Hit ratio = 12/18

More Related