Viney Kumar and Virendra Singh Indian Institute of Science Bangalore, India

1. FREP( Floating Resources Extended Pipeline):A Soft Error Resilient Pipelined RISC Architecture Viney Kumar and Virendra Singh Indian Institute of Science Bangalore, India Rahul Raj Choudhary Govt. Engg.College Bikaner, India East West Design and Test Symposium 2009 Moscow, Russia

2. Outline • Introduction of Soft error • Related work • Soft error and Embedded systems • FREP ( floating recourses extended pipeline) Concept • FREP-Pipelined RISC architecture • Instruction re-execution algorithm • Analysis • Result Discussion • Conclusion

3. Soft Error • Decreasing supply voltages and nodal capacitances (required for constraining the power and making circuit transition faster) result in reduced critical charge (Qcrit) are likely to upset a node in digital circuits. • The problem becomes more acute for aircraft and space electronics where high-energy neutrons at higher altitudes and heavy ions in space are more abundant. From P. Shivakumar et al, DSN 2002

4. Related Work Soft error detection Space redundancy Time redundancy The technique Triple Modular Redundancy (TMR) ( 2/3 logic )provides fault tolerance capability, but it has 200 percent hardware overhead .

5. Related Work Count. Micro architecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors ReStore : Symptom Based Soft Error Detection in Microprocessors

6. Soft Errors in Embedded System • Lot of Micro-architectures are proposed for superscalar machines( like AR-SMT , ReStore , REESE). • These architectures demands lots of extra hardware which is fortunately present in superscalar machines. • No soft error resilient micro-architecture is proposed for small execution engine as per our knowledge. • In future when smart sensor networks will be deployed in harsh environment , soft error resilient micro-architecture for small execution engine will be required.

7. FREP Architecture ( Floating Resource Extended Pipeline) • The fact, that all instructions do not use all the resources of any processor, can be utilized to achieve redundancy in time during execution. • Even instructions which make use of ALU, do not utilize all hardware resources of ALU. This allows division of ALU into smaller functional units like arithmetic unit, logical unit and multiplier unit. • This enables re-execution of instructions by making simultaneous usage of these functional units. • Adding extra pipeline stages between execution and commitment stage, gives more clocks cycles to instruction for re-execution without stalling the pipeline.

8. FREP Concept

9. FREP-Pipelined RISC Architecture • MIPS Architecture • 10 pipeline stages • Partition of ALU in two function unit • 24 instructions ( R and I type )

10. Fetch DecoderDecoder execute re-execute re-execute re-execute re-execute memory write . compare cycle-1 cycle-2 cycle-3 cycle-4 write back Backward pipe which brings Instruction for re execution and for data forwarding Adder Sub tractor Comparator Comparator Decoder-I Data memory Instruction Memory AddInstruction 2 MOVE Instruction 1 AddInstruction 1 AddInstruction3 ANDInstruction 1 AddInstruction 3 AddInstruction 1 AddInstruction 2 ANDInstruction 1 MOVE Instruction 1 Decoder- II Register File Logical Functi-on unit Comparator Backward pipe which brings Instruction for re execution and for data forwarding

11. Key Points of FREP Architecture • In order execution • Out of order re-execution • Space – time redundancy • Data forwarding • Re execution before commitment of an instruction • Two re execution or One execution and one re execution is possible

12. Instruction Re-execution Algorithm

13. Analysis • It is assumed that memories and buses (data and address) is covered with Error detection and correction codes. • Function units are covered with time redundancy ,FREP(execution and re-execution) concept. • Decoder is covered against soft error by duplication. • All FSM are protected by virtue of their nature.

14. Analysis( count.) • All “NOP” instruction effectively converted into re-execution instructions. • Because of 10 stage pipelines load instruction forces to introduce extra “NOP”. • All “branch” instruction gives some margin to re-execute instructions.

15. Result Discussion • FREP Architecture, for soft error detection, has been validated using RTL Simulation in ModelSim. • Soft errors are injected in FU, decoders and Data forwarding FSM. • Hardware overhead of 15.2% has been observed with two functional units and 10 pipeline stages. • We carried out simulation using small embedded system programs and time overhead in re-executiong all the instructions of detection of soft error was less than 10%.

16. Conclusion • It is necessarily to account soft errors in modern systems. • Embedded systems are prone to soft errors. • We presented a low cost soft error resilient architecture .

17. Thank You