1 / 8

C. Jia, J. Bardong, C. Gruber, M . Kraft, S. Grasser

Wafer-Level Chip-Scale Packaging for Power Device Operating at High Temperature. C. Jia, J. Bardong, C. Gruber, M . Kraft, S. Grasser. CTR Carinthian Tech Research AG Competence Centre for Advanced Sensor Technologies. Enhanced Power Pilot Line.

faith-crawford
Télécharger la présentation

C. Jia, J. Bardong, C. Gruber, M . Kraft, S. Grasser

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Wafer-Level Chip-Scale Packaging for Power Device Operating at High Temperature C. Jia, J. Bardong, C. Gruber, M. Kraft, S. Grasser CTR Carinthian Tech Research AGCompetence Centre for Advanced Sensor Technologies

  2. Enhanced Power Pilot Line • Energy efficient power semiconductor devices • Setting up technologies on 300mm wafers • Demonstration of strategically selected products and technologies

  3. Motivation and Challenges • Packaging for devices working at 400°C+ • Vacuum packaging / hermetic sealing • Thermal stress reduction • Establishment of reliable electric connection • High packaging strength, good long-term reliability • Wafer-level process

  4. Schematic View of the All-Si Package bonding frame Si / glass cap metalisation Si-island chip Si-island insulation (BOX) contact pads chip carrier flexible cliper

  5. Top view of the All-Si package

  6. Hermeticaly sealed cavities of different Sizes P Si cap vacuum Dummy carrier Cross sectional view before annealing

  7. Interferometriccharacterisation Downward deformation of the vacuum-indicating membrane confirms hermeticity Static deformation of a square silicon membrane after annealing at 600°C for 30h

  8. Innovation through Cooperation

More Related