1 / 27

Lecture 13

Lecture 13. Flip-Flops Section 5.4. Schedule. Please bring a functional random number generator to class on Thursday (3/13). Outline. Review D latch Applications Flip-flops D flip-flops Reset JK flip-flops T flip-flop. D Latch . Using a Latch as a Memory Element.

fell
Télécharger la présentation

Lecture 13

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Lecture 13 Flip-Flops Section 5.4

  2. Schedule Please bring a functional random number generator to class on Thursday (3/13).

  3. Outline • Review • D latch • Applications • Flip-flops • D flip-flops • Reset • JK flip-flops • T flip-flop

  4. D Latch

  5. Using a Latch as a Memory Element Caution for a D latch: once a clock enables a D latch, the output changes as soon as the input changes – this is not desirable if you do not want the output to change continuously and all the latches use a common clock.

  6. Uses of Flip-flops

  7. D Flip-Flop

  8. Negative Edge triggered D Flip-FlopClk=1 Y=D hold 1 0

  9. Negative Edge triggered D Flip-FlopClk=0 Q=Y hold 0 1

  10. Negative Edge triggered D Flip-FlopClk=1 1 Y=1 0 hold 1 0

  11. Negative Edge triggered D Flip-FlopClk=0 1 0->1 Q=Y hold 0 1

  12. Verilog Modeling I1 I2

  13. Positive Edge Triggered D Flip-flop I1 I2

  14. D-Type Positive Edge Triggered Flip-Flop (CLK=0) 1 0 1 0 CLK =0, maintain the present state

  15. D-Type Positive Edge Triggered Flip-Flop D=0 as Clk=0→ 1 1 0 1 0→1 1 → 0 0 1 Q changes to 0

  16. D-Type Positive Edge Triggered Flip-Flop D=1 as Clk=0→ 1 0 1 1 → 0 0→1 1→ 1 1 0 Q changes 1

  17. D-Type Positive Edge Triggered Flip-Flop D=0→ 1 as Clk=1 1 S’ S 1 S’ The flip-flop is unresponsive to changes in D 0 → 1 1 Please explore different possible value of S on your own. This will work even for S=R=1 and S=R=0. revise

  18. Symbol of D Flip-Flops

  19. reset and preset • When power is first turned on, the state of the flip-flops is unknwon. • Reset is used to initialize the output to a 0. • Preset is used to initialize the output to a 1.

  20. Reset Feature 1 0 1 0 0 When Reset is 0, Q is set to 0.

  21. D Flip-flop with reset Typo in the book. Should be 1 instead.

  22. JK Flip-Flops D=JQ’+K’Q Positive edge D flip-flop The next value of D is determined by JQ’+K’Q. At the rising edge of D Flip-flop, Q is updated with the value of D.

  23. D=JQ’+K’Q • J=1,K=1→D=Q’ • J=0, K=0→D=Q • J=0, K=1→D=0 • J=1, K=0→D=Q’+Q=1

  24. Verilog Implementation

  25. T Flip-Flop

  26. T Flip-Flop from D Flip-Flop DT rst D=TQ’+T’Q If T=1, D=Q’ If T=0, D=Q. Q is updated with D at the next rising edge.

  27. Verilog Implementation of a T-FF DT rst

More Related