David O’Hallaron

1. Processor Architecture Overview David O’Hallaron Carnegie Mellon University http://mprc.pku.edu.cn/ics/ Based on original lecture notes by Randy Bryant, CMU

2. Course Outline • Background • Instruction sets • Logic design • Sequential Implementation • A simple, but not very fast processor design • Pipelining • Get more things running simultaneously • Pipelined Implementation • Make it work • Performance optimization • Performance analysis • High performance processor design

3. Coverage • Our Approach • Work through designs for particular instruction set • Y86---a simplified version of the Intel IA32 (a.k.a. x86). • If you know one, you more-or-less know them all • Work at “microarchitectural” level • Assemble basic hardware blocks into overall processor structure • Memories, functional units, etc. • Surround by control logic to make sure each instruction flows through properly • Use simple hardware description language to describe control logic • Can extend and modify • Test via simulation • Route to design using Verilog Hardware Description Language • See Web aside ARCH:VLOG

4. Schedule • Week 1 • Y86 instruction set architecture • Logic design • Sequential implementation Assignments: Part A: Write & test assembly code programs Part B: Add new instructions to sequential implementation • Week 2 • Pipelining and initial pipelined implementation • Making the pipeline work • Performance optimization on modern systems Assignment: Part C: Optimize program+pipeline for max performance

5. Textbook • Randy Bryant and David O’Hallaron, “Computer Systems: A Programmer’s Perspective, 2nd Edition”, Prentice Hall, 2011. • Topics covered: • Processor Architecture (Chapter 4) • Performance Optimization (Chapter 5) • Assumes prior knowledge of x86 assembly (Chap 3)