1 / 9

PHOBOS Trigger Logic

PHOBOS Trigger Logic. L0 Logic. All times are relative to PNPP wide. R. Connected to a register. N. Connected to a scaler. Twisted pair dECL lines. 55. 108. 206. 60. 210. G12.10. G12.5. G5.10. G5.09. G12.4. G12.6. G5.09. G5.09. G12.2. G12.3. G12.1. C2.14. C2.10. C2.11.

field
Télécharger la présentation

PHOBOS Trigger Logic

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. PHOBOS Trigger Logic A. Sukhanov

  2. L0 Logic All times are relative to PNPP wide R Connected to a register N Connected to a scaler Twisted pair dECL lines 55 108 206 60 210 G12.10 G12.5 G5.10 G5.09 G12.4 G12.6 G5.09 G5.09 G12.2 G12.3 G12.1 C2.14 C2.10 C2.11 C2.09 C2.13 C2.12 C2.16 4 ns 4 ns 64 ns 43? 44 288 220us 44 164? 408 124 1800us 56 FI 68 452 G9.B 114 26 ns D D C C D G6C G11C G11B G6A G6B C Measured Pause Interval for pileup control TML0 MPI 1/N R R N TOF ADC GateCAT ADC Gate 1/N R CO.2 1/N R CO.5 CC 1/N R Paddle ADC Gate ADC 6 R d Trig TDC C3.16 L0Pulse R ZCAL+PaddlesTDC Start TDC 4+5 1 CO.1 R TOF+PaddlesTDC Start CAT ICAS N R N L0 Time=0 L0 to L1 L1CI.0 CO.0 ! R Heartbeat Veto L0 74 R Pedestal N Busy from L1 L1C0.15 R CI.15 Si Cosmic Busy from FB. NIMOUT 0 R ZGate PNPP Wide d ZCAL ADC Gate ADC 7 CO.3 D R ZExclGate ZCAL C 2520 in the case of FC 2 ms normal CO.4 CO.10 L0 FanOut CO.11 Non ZCAL trigger R TOF Cal CO.8 Exclusive ZCAL trigger PCAL main gate CO.9 PCAL cosmic gate Changes: 8/28/00 front of the ZCAL ADC made earlier by 16 ns 11/02/00 TOFrig applied to G11C bypassing 40ns delay to gain 40 ns for TOF cosmic 11/13/00 Drawing error, swapped C2.10<->C2-11 7/04/01 G12 input changes to fit the flat cable arrangement 7/05/01 Paddle ADC Gate G12.3-G6B cable delay changed from 48 to 16ns. G6B changed to 140ns 7/06/01 Paddle ADC Gate G12.3-G6B cable delay changed from 16 to 4ns. G6B changed to 152ns 11/13/02 Paddle ADC Gate G6B is taken from G12.2 not G12.6. 11/14/02 Added MPI, prescalers T[0:3] 01/10/03 Added PCAL gates A. Sukhanov

  3. L1 logic 1000 1060 55 1 D 526 114 2520 5000 G12.13 C D D C C G11A R Connected to a register N Connected to a scaler TML1 Twisted pair dECL lines 1/N Prescaler 0.0-3 L0from G11B 0 R 1/N Pn*Pp(2)from A8B 1 0.4-7 R R N 1/N Fast Clear CO.2 ZTrigfrom D7C 2 0.8-11 R 1/N Busy Pn*Pp Narrowfrom A2B 3 0.12-15 Veto to L0 R CO.15 1/N L1 N L1 to EMS Silicon (CI.0) Vtxfrom A10B 4 3.0-3 CO.1 R 1/N Centralityfrom A12B 5 3.4-7 R 1/N Event Accepted R N L1 CVtxfrom A12A 6 3.8-11 CO.0 R L1 to DAQ (EMM.CI.0) 1/N 3.12-15 Trig TDC (C3.8) Heartbeatfrom C10C 7 R 1/N Note. Before 07/12/00 the G11A output has been at 180 ns Changes: 5/29/01. Drawing error. G11B to G11A 7/4/01. G12.13, CO.2 PN*PP wide PN*PP narrow L0 Fast Clear L1 A. Sukhanov

  4. EMM 7) 0)Trig0 1) 2) 3) 5)Veto1 6)Done1 8)MDCL2 4)Trig1 10) 12) 13) 14) 15) Veto 16) GND 11) 9)SynCal 09) Token6 08) Token7 15) Token0 14) Token1 13) Token2 12) Token3 11) Token4 07) TokStrobe 10) Token5 04) Trig Pulse 16) GND 06) HShk 01) HShk 05) CO5 00) Busy 03) SiL2 02) SiL1 02) 03) 04) 01) 06) 07) 05) Red Orange Yellow Green Blue Purple G11B + Cin - - Cout + To VMERocand FastBus + G5 - SiL2, SiL2 G8.2:3 BusyEMM. G9.3 SiL1, SiL1 G8.0:1 A. Sukhanov

  5. TML0 and TML1 0) 1) 2) 3) 15) Veto 6) 14) CC 4) 9) FBCosm 10) 100 Hz 11) SiCosm 12) PNPP 13) ZTrig 7) 8) Heartbeat 11) 5) 13) 16) GND 12) 10) 9) 8) 7) Pr7 6) Pr6 5) Pr5 15) Veto 3) Pr3 2) Pr2 1) Pr1 0) Lvl0 14) 16) GND 4) Pr4 7) TinV 6) HiPrio 5) FBCosm 4) ZGateExcl 3) ZGate 2) L0 pulse 1) L0 pulse 16) GND 16) GND 13) PrO.6 15) Busy 0) Lvl1 1) L1Pulse 3) L1in 12) PrO.5 14) PrO.7 8) Tin 9) 0 10) 0 11) PrO.4 5) PrTest 10) PrO.3 9) PrO.2 7) PrO.0 6) L1OR 4) PrQ1 8) PrO.1 2) FastClear 15) Veto L0 14) 13) 12) 11) 0 0) L0 + Cin - + Cin - CC clocked triggers - Cout + - Cout + TinV G12 08 HiPrio 07 TOF Excl ADC Gate 06 ZCAL ADC Gate 05 PrQ1 G12 16 ZCAL ADC Gate 04 L1in 15 TOF+Paddle ADC Gate 03 Fast Clear 14 02 L1pulse 13 Paddle+ZCALTDC start 01 L1 12 To L1 logic, TOF TDC start A. Sukhanov

  6. Si L0/L1 73us 73us 41us 41us G12.11 G8.12 G12.9 G8.13 G8.15 G8.14 G8.0 G8.3 G8.2 G8.1 G5.4 G5.3 560us 2560us G7C G7D G4D Calibration mode Time=0 TTL/NIM NIM/ECL EMM MDC1 SynCal MDC1 L1 Si L1 CI.9 CO.2 MDC2 L1 MDC2 SynCal MDC1 L2 MDC1 INT L2 Si L2 CO.3 CI.8 MDC2 L2 MDC2 INT L2 A. Sukhanov

  7. NIM Crates G12 Model 4616 To L1 logic, TOF TDC start L0 01 Paddle+ZCALTDC start 02 TOF+Paddle ADC Gate 03 ZCAL ADC Gate 04 ZCAL ADC Gate 05 TOF Excl ADC Gate 06 HiPrio 07 TinV 08 SynCal 09 Busy L1 10 MDC* 11 L1 12 L1 L1pulse 13 Fast Clear 14 L1in 15 PrQ1 16 A. Sukhanov

  8. FASTBUS LEMOs LEDs G L1 Busy NIM In 1 R L2 Error 2 G L3 EMMData 3 G L4 Init Reset NIM Out 1 Busy 2 Error 3 Data Transfer Description Legend: L refers to LED, N – to NIM LEMO L4 ON: init_crate OFF: Run stopped N2 L2 : 1: 1)Read/Write mismatch, slot %d (r=%d,w=%d). DP=%x 2)ERROR: Load Next Event in slot %d\n",slot 0: Finished sending event L3: 1: start copying VME block8 0: finished VME block N3, L4 1: Start sending event 0: Finished sending event N1,L1 1: End of the Sparse Data Scan 0: Finished VME block A. Sukhanov

  9. Modifications 1/1/4. Cosmetic A. Sukhanov

More Related