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On the Design of a Photonic Network-on-Chip

Presented for HPCAN Session by : Millad Ghane. Assaf Shacham , Keren Bergman, Luca P. Carloni. On the Design of a Photonic Network-on-Chip. NOCS’07. Why NoC ?. Scaling Transistor Speed and Integrity Tighter Logic Power Dissipation Increasing Number of Cores per Chip

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On the Design of a Photonic Network-on-Chip

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  1. Presented for HPCAN Session by: Millad Ghane AssafShacham, Keren Bergman, Luca P. Carloni On the Design of a Photonic Network-on-Chip NOCS’07

  2. Why NoC ? • Scaling Transistor Speed and Integrity • Tighter Logic • Power Dissipation • Increasing Number of Cores per Chip • Bottleneck: Global Intrachip Communications • Bandwidth • Power • Performance-per-watt

  3. Why Optic ? • Low Power Dissipation • Ultra-high Throughput • Minimal Latency • End-to-end Transmission • No Repeating • No Regeneration • No Buffering A silicon ring resonator

  4. Hybrid Architecture • Photonic Interconnection • High Bandwidth Messages • Electronic Interconnection • Low Bandwidth Messages • Short Control Messages

  5. Photonic Properties • Advantages • Bit-rate Transparency • Not Switching by Every Bit of Data • Switching Once per Message • Low Loss in Optical Waveguide • Independence of Transmission Distance • Disadvantages • No Storage Element • E/O and O/E Conversions • Off-chip Lasers

  6. Packet Life Optic Network Electronic Network D D S Sending path-setup packet S

  7. Packet Life D D S Sending optical packet S

  8. Packet Life D D S Sending path-teardown packet S

  9. Packet Life D D S Sending path-blocked packet S path-teardown packet

  10. Building Blocks 70 µm Photonic Switching Element 70 µm Electrical Router

  11. Building Blocks Problems • No Injection/Ejection Port • Not Deadlock-Free • Wide Turns

  12. Approach Ejection Switch Injection Switch Gateway Switch Torus Network Nodes Access Points Address Format

  13. Deadlock Solution • Injection-Ejection Blocking • [previous slide] • Intra-dimentional Blocking (Torus Network) • Virtual Channel Flow Control • Circuit Switching • terminate-on-timeout packet

  14. Simulation Parameters • POINTS Simulator • Based on OMNET++ • 36-core CMP • 6x6 planar • Chip size: 20 x 20 mm • Uniform Traffic • 3 Cases • Deadlock • Message Size Optimization • Increasing Path Diversity 2

  15. Message Size Optimization • Long path-setup latency • Nonoseconds • Super fast transmission Overhead Ratio:

  16. Message Size Optimization (cont.) • Message Duration: 50ns • Message Size: 2KB Suitable for DMA Trans

  17. Increasing Path Diversity • PD=2 • Less Hardware • Less OverheadDifference

  18. Q & A ? Thanks !

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