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ITRS 2001 Factory Integration Chapter Probe/Test Manufacturing Backup Section

ITRS 2001 Factory Integration Chapter Probe/Test Manufacturing Backup Section. Details and Assumptions for Technology Requirements and Potential Solutions. Backup Outline. How Metrics were Selected Disruptive Test Technologies Probe/Test Manufacturing Technology Requirements Table

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ITRS 2001 Factory Integration Chapter Probe/Test Manufacturing Backup Section

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  1. ITRS 2001 Factory Integration Chapter Probe/Test Manufacturing Backup Section Details and Assumptions for Technology Requirements and Potential Solutions ITRS Factory Integration TWG

  2. Backup Outline • How Metrics were Selected • Disruptive Test Technologies • Probe/Test Manufacturing Technology Requirements Table • Translating Probe/Test Manufacturing Technology Requirements to Reality • Supporting Material for Probe/Test Manufacturing Technology Requirements ITRS Factory Integration TWG

  3. How Test FI Metrics were selected • Limited scope to metrics that targeted integration time and product set up time improvements • Equipment Integration and Product Setup benchmark data from other areas of semi-conductor manufacturing is readily available (i.e. Wafer Fabrication, Package Assembly) • Technical expertise is readily available to derive viable improvement targets • Use relative values rather than absolute values • Protect IC Manufacturer competitive info. • Protect ITRS Test TWG and SEMATECH Test Benchmarking Project member competitive info. • Test metrics are not necessarily tied to the technology nodes as in other chapters such as Lithography • However, nodes offer convenient interception points to bring in new capability, tools, software and other operational potential solutions • Inclusion of each metric is dependent on consensus agreement We think the metrics provide a good summary of stretch goals for most companies in today’s challenging environment. ITRS Factory Integration TWG

  4. Name Company Role Paul Patton Advantest Product Manager Roy Odhner Agere Probe and Test Equipment Control and Data Collection Bill O’Grady Agilent Automated Test Group Factory Automation Program Manager Kazu Nishitsuru Agilent Agilent ITRS representative Clift Richardson Delta Automated Products Group Technical Lead David Barton Gem City Controls and Software Engineering Manager Duane Howard IBM 300mm Backend Software Program Manager Steve Stringer IBM IBM SEMI Standards Expert Agnes Kwan Intel Logic Technology Development Automation Pathfinding Manager Rohan Nageswaran Intel Wafer/Package Test Equipment Control Manager Don Hartman Motorola Front End Probe and Test Automation Andreas Piependrink Multitest Electronics Engineering Manager Peter Kaul Multitest Electronics Development Gino Crispieri SEMATECH 300mm Project Manager for Front End Standards Jim Ammenhauser SEMATECH Project Manager Test Benchmark Committee Atlant Smith Teradyne Semiconductor Test SW Lead Developer Jim Schillawski Teradyne Semiconductor Test SW Lead Developer Tony Auwn Teradyne Semiconductor Test SW Manager ITRS Test FI Team Membership(8/3/01) ITRS Factory Integration TWG

  5. Impact of Key Technologies to Test ITRS Factory Integration TWG

  6. ITRS Test Factory Integration Technical Requirements Table • Test Product Changeover Notes / Assumptions: • No known solutions for targeted improvements from 2004 and beyond (Industry Action is Required) • Expect to see larger improvements in complex devices vs. simple devices due to • significantly longer Test Program download and compile times. • Test Equipment Integration Notes / Assumptions: • No known solutions for targeted improvements from 2005 and beyond. • Expect to see larger improvements in 1st article equipment integration due to the usage of 3rd party SW and • industry developed test plans. • Improvement targets are based on known SECS/GEM equipment integration times relative to Test. ITRS Factory Integration TWG

  7. Translating Test metrics to Reality ITRS Factory Integration TWG

  8. Driven by SEMI Test SEM Revision Task Force Potential Solution Roadmap Driven by SEMATECH Test Interface Standards Focus Group Glossary Research Required covers the requirements gathering, problem definition and potential solution discovery activities required to address a specific technology requirement. Legend Development Underway covers the requirements gathering, analysis, design, implementation and testing of standards compliant software and hardware systems. Qualification / Pre-Production covers the high volume factory insertion and ramp of product on standards compliant HW and SW systems. Probe/Test Manufacturing Potential Solutions ITRS Factory Integration TWG

  9. Legend: ICM Owned SW Supplier Owned SW HW Boundary Factory Information and Control System “Setup / Init” MES, Equipment Control and Equipment Engineering Systems 1a “Start Lot” 2 HSEM (E30.2) PSEM (E91) Proc Mgmt (E40) Ctrl Job (E94) Carr Mgmt (E87) Subs Trk (E90) Mat Handoff (E84) “EOT” TSEM (E30.3) Proc Mgmt (E40) Ctrl Job (E94) 3b “End Lot” “Index to Next Unit” 4a 3c “End Lot Complete” Next Gen Prober / Handler Tester SECS/GEM Interface 4c Prober/Handler SECS/GEM Interface Supplier Internal Calling Mechanism TESTER OS “Open Datalog” “Write Unit Data” “Close Datalog” NEW Test Result Format and Transport Standard 1c 3a 4b Test Program NEW Test Process Program Content Standard (Exx.yy) Network File Server “TestProgram Load” Next Gen Tester Test Program NEW Test Process Program Transport Standard (Exx.yy) 1b Test Equipment Control and Data Collection “Vision State” Architecture ITRS Factory Integration TWG

  10. Test Equipment Control Architecture Alternatives Claims of Intent • The following 4 architecture alternative diagrams are not mandates for compliance with the TSEM, HSEM or PSEM standards. • The purpose of the diagrams is to illustrate potential implementations of the TSEM, HSEM and PSEM standards. • i.e. the TSEM, HSEM and PSEM standards should not preclude any one of these architectures. • It is left up to the IC Manufacturer and Supplier to negotiate and choose their mutually preferred architectural implementation. ITRS Factory Integration TWG

  11. Legend: IC Manu Owned SW Vendor Owned SW HW Boundary Manufacturing Execution System Factory MES Server(s) IC Manufacturer Proprietary Interface • Notes: • The diagram does not intend to imply a specific physical network topology. • One or more physical network connections may emanate from each HW boundary. • GJG refers to all applicable GJG SW standards to a particular piece of equipment. Test Cell Host 2 Test Cell Host 1 Workstation / PC Workstation / PC HSEM/PSEM + GJG HSEM/PSEM + GJG TSEM + GJG TSEM + GJG Prober/Handler 2 Prober/Handler 1 Tester 2 Tester 1 Workstation / PC Workstation / PC Workstation / PC Workstation / PC Test Equipment Control Architecture Alternative 1 ITRS Factory Integration TWG

  12. Legend: IC Manu Owned SW Vendor Owned SW HW Boundary Manufacturing Execution System Factory MES Server(s) IC Manufacturer Proprietary Interface • Notes: • The diagram does not intend to imply a specific physical network topology. • One or more physical network connections may emanate from each HW boundary. • GJG refers to all applicable GJG SW standards to a particular piece of equipment. Test Cell Host 1 Test Cell Host 2 TSEM + GJG TSEM Tester 1 Tester 2 Workstation / PC Workstation / PC Prober/Handler 2 Prober/Handler 1 HSEM/PSEM + GJG HSEM/PSEM + GJG Workstation / PC Workstation / PC Test Equipment Control Architecture Alternative 2 ITRS Factory Integration TWG

  13. Legend: IC Manu Owned SW Vendor Owned SW HW Boundary Manufacturing Execution System Factory MES Server(s) IC Manufacturer Proprietary Interface • Notes: • The diagram does not intend to imply a specific physical network topology. • One or more physical network connections may emanate from each HW boundary. • GJG refers to all applicable GJG SW standards to a particular piece of equipment. Test Cell Host 1 Test Cell Host 2 HSEM/PSEM + GJG HSEM/PSEM + GJG Handler/Prober 1 Handler/Prober 2 Workstation / PC Workstation / PC Tester 2 Tester 1 TSEM + GJG TSEM + GJG Workstation / PC Workstation / PC Test Equipment Control Architecture Alternative 3 ITRS Factory Integration TWG

  14. Legend: IC Manu Owned SW Vendor Owned SW HW Boundary Manufacturing Execution System Factory MES Server(s) IC Manufacturer Proprietary Interface Test Cell Host 1 Test Cell Host 2 HSEM/PSEM + GJG HSEM/PSEM + GJG TSEM + GJG TSEM + GJG Handler/Prober 1 Tester 1 Handler/Prober 2 Tester 2 Workstation / PC Workstation / PC • Notes: • The diagram does not intend to imply a specific physical network topology. • One or more physical network connections may emanate from each HW boundary. • GJG refers to all applicable GJG SW standards to a particular piece of equipment. Test Equipment Control Architecture Alternative 4 ITRS Factory Integration TWG

  15. Unit Test Cycle SC Performance Eqp Vendor/Eng Scope 2 3 5 1 6 7 8 4 Test Cell Communication Model • Unit Test Time component breakdown: • SC processing (Index to next unit) • SC – handler/prober communication (Index to next unit) • Handler/prober indexing • SC – handler/prober communication (Ready to Test) • SC processing (Start Test) • SC – tester communication (Start Test) • Test Program execution • SC – tester communication (End Test) Automation/IT Scope Eqp Vendor Scope Automation/IT Scope Engineering Scope Automation/IT Scope ITRS Factory Integration TWG

  16. 3 SW Possible Deployment Models: • SC lives on Tester HW • SC lives on Prober/Handler HW • SC lives on separate HW SC processing (Index to next unit) SC – handler/prober communication (Index to next unit) Handler/prober indexing SC – handler/prober communication (Ready to Test) SC processing (Start Test) SC – tester communication (Start Test) Test Program execution SC – tester communication (End Test) Test Cell Business Logic 5 1 Tester Communication Flow Prober/Handler Communication Flow 4 8 2 6 Prober/Handler Controller Tester PLC Equipment Interface 7 3 Prober/Handler Equipment Tester Equipment GPIB Non Standard Test Equipment Control Communication Model(s) - (Non Standard) ITRS Factory Integration TWG

  17. Station Controller PC 5 1 Test Cell Business Logic SC processing (Index to next unit) SC – handler/prober communication (Index to next unit) Handler/prober indexing SC – handler/prober communication (Ready to Test) SC processing (Start Test) SC – tester communication (Start Test) Test Program execution SC – tester communication (End Test) Tester SECS/GEM Driver Handler SECS/GEM Driver Tester Communication Flow Prober/Handler Communication Flow OS TCP/IP Protocol Stack 8 6 4 2 10/100BaseT Ethernet Network HSMS/SECS/GEM/HSEM/PSEM HSMS/SECS/GEM/TSEM New Datalogging Standard External Factory Systems and Storage Tester Embedded Control Logic Prober/Handler Embedded Control Logic 7 3 Tester PC External Servers Prober/Handler PC Proposed Test Equipment Control Model ITRS Factory Integration TWG

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