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Control Session Summary

This summary focuses on the main issues and safety of the detector in the VELO Control Session, including the use of PLCs for process control and interface with the LHC machine. The requirements, interfaces, and data volume for sub-detectors are also discussed. Additionally, potential board-level interfaces and control infrastructure options are explored.

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Control Session Summary

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Presentation Transcript

  1. Control Session Summary (Or what I understood from it)

  2. VELO Control • Systems to be controled • Motors, Vacuum, Cooling • Main Issues • Safety of the Detector • PLC’s for “process control” • Interface with LHC machine • Close contact with the LHC vacuum people • HW signals not well defined yet • Interface to LHCb ECS • The PLC’s will be controlled by the SCADA FW

  3. Requirements from Sub-detectors • Nr. Of Boards • ~8000 (many of each are quite small) • Mostly Outer tracker and Muons • Nr of Crates (no need for VME) • 150 - 200 • Needed Interfaces: • I2C, JTAG and some form of a parallel Bus • Serial, IO lines also used • Data Volume (mainly for configuration) • from a few bytes to a few MegaBytes • We would like more information • Radiation doses and what boards sit where

  4. Chip-level (or small boards) Interface • CCU Rings (S. Marchioro for CMS tracker) • I2C, JTAG, 8 bit parallel bus (plus timing signals) • Radiation hard • Long Distance I2C/JTAG • both are feasible and very simple • No problem with radiation damage • Potential grounding problem • Daisy chain ? ( bus Problem)

  5. Etc... ADCs TDCs FPGAs Regs LUTs Controls Interface I2C PCI Bus Parallel Bus DSPs JTAG Board-level Interface E.g. 9Ux400mm I/O I/O • Configuration • Monitoring • Diagnostics • Debugging • ... Power Connectors WS Field-bus Reset Note: No other interface!! Standard Application Specific

  6. Board-level Interface • Possible green box Implementations: • Credit-Card PCs • Provides all required on board interfaces • Provides enough bandwidth • Not Radiation-Hard (should be tested) • Good for boards in the barracks • Fire wire • Enough bandwidth • Don’t know if it’s feasible yet • Not Radiation-Hard (but maybe simpler?)

  7. Board-level Interface • Other Possibilities: • CCU Rings • Not enough bandwidth • Save Look Up tables and FPGA code on EEPROM ? • Not enough address space (on the board) • Very slow and cumbersome software on “Supervisor” ? • More design effort on each board • Fieldbuses (CAN or Profibus) • Same as for CCU rings • Not Radiation-Hard controllers • Just I2C/JTAG ? Dominique Breton will make a proposal for Milano

  8. General Control Infrastructure • The Generic Architecture was presented • Hierarchical, homogeneous (still Preliminary) • A framework will be available • Based on a SCADA system (JCOP) • It will provide: • Tools to interface to HW Devices • Pre-implemented Components for “Standard” solutions • Tools to implement the Hierarchical Entities • Partitioning, alarm handling, User Interfacing

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