Status of the Silicon Strip Detector/ FEE development

1. Status of the Silicon Strip Detector/ FEE development E. Atkin Moscow Engineering Physics Institute (State University) – MEPhI, M. Merkin, A.Voronin Skobeltsyn Institute of Nuclear Physics / Moscow State University–SINP / MSU, V. Saveliev State University, Obninsk CBM Collaboration meeting October 6-8, 2004

2. New Si-Strip STS Geometry by V. Saveliev New Geometry of the Si-Strip STS 4 Si-Strip Planes inside the Magnet ( equivalent distances along z ) STS_7 STS_6 STS_5 STS_4 z Significantly Reducing the Requirements for the Si-Strip STS Design ( STS_3 is MAPS technology ) 100 cm 80 cm y 60 cm x 40 cm CBM Collaboration meeting, October 6-8, 2004

3. Double Sided Si-Strip Detectors Thickness : 100 mkm Pitch of strips : 25 mkm Stereo Angle : 15o Inner region of Si-Strip STS: 25 mkm Pitch gives 400 strips per cm According the occupancy plots for STS_4: 10 Point per cm per event, or 2.5 % for 1 cm length strip 17 Point per cm per event, or 4.2% for 2 cm length of strip Basic Technology of Si-strip STS by V. Saveliev CBM Collaboration meeting, October 6-8, 2004

4. Basic Elements: Inner : 6x4 cm Middle : 6x12 cm Outer : 6X20 cm Si strip STS_6 Layout(layer 6) +40 cm by V. Saveliev +4cm - 4cm -40 cm Read out CBM Collaboration meeting, October 6-8, 2004

5. Silicon Sensors: What we have • 15 years experience in sensor design and production; • Experience in double side photolitography, first prototype for ATLAS SCT; • Good new mask aligner for double side photolitograpy (up to 6”) CBM Collaboration meeting, October 6-8, 2004

6. Silicon Sensors: What we have • Fine pitch (25 µm) sensors have been designed and produced for SVD-2 experiment at Protvino; • Radiation hard sensors designed, prototypes produced and tested up to 8 MRad for D0 RunIIb; • Almost all equipment for sensor testing. CBM Collaboration meeting, October 6-8, 2004

7. Silicon Sensors: What we need • We need to know physics requirements for sensor geometry; • Estimation of radiation environment(!!!); • Estimation of temperature inside tracker; • Long term scenario: possible warm-cold circles, estimated detector life time – 5 years(?), 10 years(?); CBM Collaboration meeting, October 6-8, 2004

8. Silicon Sensors: What we can do • Photomask design as soon as geometry will be clear; • Several geometries of sensors could be on the same mask; • Sensor prototypes production; • Full electrical sensor testing; • Radiation testing (with KRI). CBM Collaboration meeting, October 6-8, 2004

9. Silicon Sensors: Cost estimation • Double side polished silicon wafers: • 300 µm – 25 wafers (for tests only) • 200 µm – 50 wafers; (for prototype • 150 µm – 50 wafers; production) • 100 µm – 50 wafers. Total wafers cost – 4000 ÷ 6000€ Depends on resistivity and supplier CBM Collaboration meeting, October 6-8, 2004

10. Silicon Sensors: Cost estimation • Photomasks design and production. For double side sensors we need 14 or 15 photomasks. Cost is about 500 - 600 €/mask. Total masks price: 7000 ÷ 9000 € CBM Collaboration meeting, October 6-8, 2004

11. Silicon Sensors: Cost estimation • Sensor production cost (prototypes): • 300 µm –    600 €/wafer; • 200 µm –    700 €/wafer; • 150 µm –    800 €/wafer; • 100 µm –    850 €/wafer. !!! This is not a sensor cost !!! It might be a lot of sensors on wafer, total active area ~36 cm2 CBM Collaboration meeting, October 6-8, 2004

12. Silicon Sensors: Cost estimation • Tools and fixtures for testing (? €); • Testing - 1 man*day/sensor (25 €); • Cutting – few € per wafer depends on number of cuts; • Second testing (after cutting) - 1 man*day/sensor (25 €). CBM Collaboration meeting, October 6-8, 2004

13. Silicon Sensors: Schedule • Photomasks design and production - 3 months; • Sensor prototype production: • 300 µm – 10÷15 wafers - 4 months; • 200 µm – first 10 wafers - 4 months; • 200 µm – second 10 wafers – 2 months; • 150 µm – first 10 wafers -3 months; • 150 µm – second 10 wafers -2 months; • 100 µm – first 10 wafers -3 months CBM Collaboration meeting, October 6-8, 2004

14. Silicon Sensors: Schedule In total according to this optimistic schedule we will have about 50 wafers with different sensors in 12 – 14 months. Two last months are mainly for testing sensors. Radiation tests could be started on the first batches of 10 sensors. CBM Collaboration meeting, October 6-8, 2004

15. Silicon Sensors: Schedule Pessimistic case: • no money; • mistakes in sensor design (second set of masks needs to be made); • problems with thin wafers. Approximately 20 - 24 months for the whole project, including radiation tests CBM Collaboration meeting, October 6-8, 2004

16. Specifications for the silicon strip detector chip • Minimal signal – 7000 electrons per mip (100um detector thickness) • Detector capacitance can be 30-300 pF depending on thickness and length of the strip, as follows from the simulation and design of tracker at a suitable signal/noise ratio • Signal noise ratio – better than 10 for 1 mip • Dynamic range (?) – 10 mips • Input signals come at random time. Maximal average frequency of the signal at the chip input is 10 MHz • Radiation hardness – 15-20 MRad • Power consumption, as small as possible. The maximal one – few mW/channel • Supply voltages depend on the technology • Number of channels on the chip is dictated by tracker design (128, 256,….) • Minimal number of external components CBM Collaboration meeting, October 6-8, 2004

17. AC detector-input coupling with a possible DC one for (?) detector dark current management • Input overvoltage protection. It must not increase noise. • Input pad pitch – 25-100 um • Connection between the chip and detector – (?) by bonding, bumping, gluing to the designed tracker • back contact – (?) insulated or VSS • Base line stability (?) • Linearity (?) • Working temperature – (?) 0-50˚C CBM Collaboration meeting, October 6-8, 2004

18. Main Features • Amplitude measurement • Time of event • Digitization of amplitude and time • Dead-time free • No external trigger • Calibration (test) system • Flexibility of control and adjustment CBM Collaboration meeting, October 6-8, 2004

19. Chip general structure • Analog part • ADC • Digital part • Control • Calibration (test) system How to realize the chip? • Completely self-triggered or signal finder built-in • Synchronizing with external clock – 5-100 ns • ADC resolution (?) – 4-6 bits for amplitude, 6 bits for time (resolution – few ns) • Signal processing – analog shaping (?) 10-30 ns, digital signal shape analyzing • Data processing – maximal data reduction and compression CBM Collaboration meeting, October 6-8, 2004

20. Biasing for Si detector and its readout scheme To next stage To next stage To amplifier CBM Collaboration meeting, October 6-8, 2004

21. Structure 1 Polarity Switch Input protection CR-RCn Shaper (n=2) Soft Limiter Scale amplifier CSA To ADC Ccal Limitation adjustment Feedback adjustment Peak time adjustment Gain adjustment Switch array Fast shaper T-Pulse DAC array Analog finder Test data DAC Threshold Calibration (test) System CBM Collaboration meeting, October 6-8, 2004

22. Pedestal subtraction Data reduction Noise reduction Zero suppression ADC Buffer Pedestal memory Shape reconstruction Interface (serial) Amplitude & Time reconstruction Pedestal calculator Signal finder Internal pulser (phase control) Pedestal measurement mode Structure 1 External CLK (second part) Control CBM Collaboration meeting, October 6-8, 2004

23. Structure 2 Polarity switch Input protection CR-RCn shaper (n=2) Peak detector Pipeline CSA To ADC Ccal Delay (adjust.) Feedback adjustment Peak time adjustment From pulser Switch array Fast shaper T-Pulse DAC array Analog finder Test data DAC Threshold Calibration (test) System CBM Collaboration meeting, October 6-8, 2004

24. Pedestal subtraction Data reduction Zero suppression ADC Buffer Pedestal memory Interface (serial) Time measurement Pedestal calculator Internal pulser (phase control) Pedestal Measurement Mode Structure 2 To pipeline External CLK (second part) Control CBM Collaboration meeting, October 6-8, 2004

25. Short resume on the aim of the ASIC • The main aim of the ASIC to be developed for CBM Si microstrip detectors is to provide both amplitude and timing (event separation) measurements • Mechanical (dimensional) fit (face-to-face) between strips and caseless ASICs • Space limitation at the detector forces to provide reasonable multiplexing to save a number of cables (communication lines) to be used • The self-triggering is an important issue • Accurate track reconstruction forces to have: • Massive parallelism of read-out • High complexity (functionality) of mixed-signal ASICs • Radiation hardness (tolerance) CBM Collaboration meeting, October 6-8, 2004

26. Technology choice • “Today 0.18…0.25 µm CMOS processes form the mainstream industrial production technologies and 0.13 µm processes are coming on-line as the next industrial generation” (P. Jarron. Trends in microelectronics and nanoelectronics and their impact on HEP instrumentation. Proc. of the 8th Workshop on Electronics for LHC experiments, 9-13 Sept. 2002, Colmar, CERN/LHCC-2002-034, p.9-16) • Probably it is expedient to add 0.25µmBi-CMOSprocesses. Bipolar is dictated by fast and precise analog blocks (like fast low-offset comparators, op amps). Usually it simplifies and shortens the design stage at the expense of more complexity of the process. • Radiation tolerant Deep Sub Micron (DSM) 0.13µm CMOS process (0.25 µm Bi-CMOS one) for prototyping and studying the possibilities seems to be the best candidate and was recommended by the 1st CBM FEE ASIC workshop at CERN on Sept. 24-26, 2004. CBM Collaboration meeting, October 6-8, 2004

27. Possible selection of manufacturers • UMC, Taiwan is the best as it was recommended by the meeting at CERN on Sept. 24-26, 2004. • IHP GmbH – Innovations for High Performance Microelectronics, Frankfurt (Oder), Germany • AMS – AustriaMicroSystems AG, Schloss Premstätten, Austria • TSMC – Taiwan Semiconductor Manufacturing Company, Hsin-Chu, Taiwan • Others CBM Collaboration meeting, October 6-8, 2004

28. In the Moscow Design Group(MEPhI* Europractice full membership number A47530) We are using mostly: • PCs and Sun Workstations • Linux and Solaris environment • Cadence tools • Europractice Design Kits • ISE TCAD tools * since 1996  Cadence software usage since 2004  Partner of Cadence/Moscow CBM Collaboration meeting, October 6-8, 2004

29. ASIC Development schedule CBM Collaboration meeting, October 6-8, 2004

30. Remarks Schedule is a quite optimistic (only two prototypes used to reach a final solution). Moscow Si-strip group also plans to develop read-out electronics for lab test purposes of the Si strips at the detector lab of MSU. Most likely it forces to design a quite fast and low noise analog chain, based on Bi-CMOS process (0.25…0.8 µm). As a main tech. process for ASIC development it is expected to use UMC 0.13 µm one with RF option. Unfortunately there is not any strategy for scaling down the ASIC design to 90 nm (or even 65 nm) processes, which will be evidently the next generation of technology era. CBM Collaboration meeting, October 6-8, 2004

31. Cost estimation for ASIC design • The ASIC design cost is consist of the following main parts: • Fabrication cost of prototype ASICs (given by e.g. Europractice) It strongly depends on process. (Currently Europractice discounted prices are 240…64000 € /mm2 typ.) • The mass (more correctly to say small volume) production cost should be comparable with prototyping cost. 1.5*106 channels ~100 channels/chip & ~1000chips/wafer  ~15 wafers only! • Designer man-power cost*. It is roughly 2..3 man*year per each prototype ASIC • Man power cost of test electronics development is about 1..2 man*year per each prototype ASIC • Man power cost of rad-had tests is about 0.5 man*year per each prototype ASIC • On the way costs for computing are estimated as a few k€ *– It is supposed, that the design group contains PhD qualified staff only CBM Collaboration meeting, October 6-8, 2004

32. MEPhI Groups • Si-strip FEE structure developmentE.Atkin, I.Ilyushchenko, A.Silaev, Yu.Volkovin collaboration with SINP/MSU (A.Voronin & oths) • ASIC designE.Atkin, A.Silaev, A.Krasniuk • IC tester designM.Alyushin, A.Alyushin, E.Onishchenko • IC rad had testsB.Bogdanovich, A.Simakov • HV fuse designA.Simakov • CBM Physics? CBM Collaboration meeting, October 6-8, 2004