Lecture 4-1 I/O Organization

Lecture 4-1I/O Organization • I/O Accesses • Interrupt in general • Next Lecture • ARM Interrupt • DMA

Accessing I/O Devices • Processor, memory and I/O devices are connected to a single bus • Bus consists of address, data and control signal lines • Each I/O device is assigned a unique set of addresses • When the processor places a particular address on the address lines, the device that recognizes the address responds to the commands issued on the address lines

Accessing I/O Devices (cont.) • The address decoder enables the device to recognize its address when it appears on the address lines

Accessing I/O Devices (cont.) • Memory and I/O addresses – two address spaces • Memory mapped I/O: I/O devices and memory share the same address space • Any machine instruction that can access memory can be used to transfer data to/from I/O devices • Example: • Move DATAIN,R0 • Move R0,DATAOUT • I/O map (separate memory map): I/O devices and memory use separate two address spaces • Special instruction (In, Out) to perform I/O transfers

I/O Examples – Keyboard and Display • The I/O operations need three registers • Data_in register holds data to be transferred to the processor from an input device • Data_out register holds data from the processor for transfer to an output device

I/O Examples – Keyboard and Display • I/O devices operate at speeds vastly different from that of the processor • We must ensure that an instruction to read a character from the keyboard is executed only when a character is available in the input buffer of the keyboard interface • We must ensure that an input character is read only once • Status register contains the two control flags SIN and SOUT • SIN: flag is set to 1 when a character is entered at the keyboard, cleared when the character is read by the processor. The synchronization between the processor and the input device is achieved by a program loop that polls the status register until SIN becomes 1. • SOUT: output synchronization flag

Programmed Controlled I/O:Keyboard and Display • Data from the keyboard are held in DATAIN until they are sent to the processor • Data received from the processor to be sent to the display are stored in DATAOUT Move #Line, R0 Initializes memory pointer WAITK Testbit #0, STATUS Test SIN Branch=0 WAITK Wait for character to be entered Move DATAIN, R1 Read character WAITD TestBit #1, Status Test SOUT Branch=0 WAITD Wait for display to become ready Move R1, DATAOUT Send character to display Move R1, (R0)+ Store character and advance pointer Compare #$0D, R1 Check for Carriage Return Branch≠0 WAITK If not, get another character Call Process Call a subroutine to process the input line

Programmed Controlled I/O:Keyboard and Display • Reads a line of characters from the keyboard, stores it in a memory buffer, calls a subroutine to process the data • Character read are echoed back to the display • R0 is used as a pointer to memory Program controlled I/O: processor repeatedly checks a status flag to achieve the required synchronization between processor and I/O device Other alternatives: interrupt, direct memory access (DMA)

Interrupt • Disadvantage of the Program-controlled I/O • The program enters a wait loop until the device is ready • During this period, the processor is not performing useful work • Other tasks can be performed while the processor is waiting • How: sending a hardware signal called an interrupt when the device is ready • At least one of the bus control lines is used for this purpose • called Interrupt Request Signal

Keyboard Input With Interrupt • Processor is doing useful computation, instead of waiting for a key pressed • Whenever a key is stroked and thus a character is ready to read, an interrupt is generated • On the interrupt, the processor is forced to process the character (may move it to a buffer or send it to the display, which is performed in an Interrupt Service Routine (ISR)) • After that, processor continues computation, which was interrupted by the key stroke • In this way, processor does not need to poll the keyboard but perform useful computation right until a key is pressed

Interrupt processing • When an interrupt occurs, the current contents of the PC must be saved in temporary storage • A Return From Interrupt (RTI) reloads the PC from the temporary storage • In many processors, return address is saved on the stack • Alternatively, it can be saved in a special location such as a dedicated register • The processor must inform the device that its request has been recognized so that it can remove its interrupt request signal: Interrupt Acknowledge Signal (INTA) Q: Differences between interrupt and subroutine? • A subroutine performs a task required by the program • An interrupt may have nothing to do with the program being executed

Interrupt processing (cont.) • Before starting execution of the interrupt service routine (ISR), any information that may be altered must be saved, such as: • return address • condition code flags • the contents of any registers to be used by the ISR • Or use another set of registers • The task of saving and restoring information can be done automatically by the processor or through program instructions

Interrupt Latency • Saving registers increases the delay between the time an interrupt is requested and the execution of the service routine: Interrupt Latency • The amount of information saved should be kept to a minimum in order to reduce the interrupt latency • Most modern processors save only the minimum amount of information that needs to preserve the integrity of program execution • Any additional information (e.g. registers to be used) must be saved by program instructions at the beginning of the service routine, and at the end of the routine it must be restored

Interrupt Enabling and Disabling • Arrival of an interrupt request causes the processor to suspend the execution of a current program • Computers provide the ability to disable interrupts • When a higher priority interrupt is serviced, a lower priority interrupt can be disabled • When a lower priority interrupt is serviced, a higher priority interrupt may be enabled or disabled • It may also be necessary to guarantee that a particular sequence of instructions is executed to the end without interruption • E.g., Interrupt should not be accepted until the control completely returns to the current program

Interrupt ProcessingProblem of Repeated Interrupt Ack • When a device activates the interrupt-request signal, it keeps the signal active until the processor accepts and acknowledges its request • The processor senses and acknowledges the interrupt • The device deactivates its request in response to the interrupt acknowledge once the service routine is executed • It is possible that the processor could respond several times to one active request • It is essential to ensure that one active request does not lead to successive interruptions => 3 alternatives

Preventing Erroneous Interrupts 1st Alternative • Have the processor ignore the interrupt-request until the first instruction of the service routine (ISR) is executed • Use an interrupt disable instruction as the first instruction of the service routine • The last instruction in the interrupt service routine enables interrupts

Preventing Erroneous Interrupts 2nd Alternative • Processor automatically disables interrupts before it starts executing the interrupt-service routine (ISR) • After saving the PC and the processor status register (PSR), it disables interrupts by masking one bit of the PSR (interrupt mask) • Interrupt is enabled by restoring the old value of PSR on a return from interrupt

Preventing Erroneous Interrupts 3rd Alternative • Arrange interrupt handling circuit in the processor such that it responds only to the leading edge of the interrupt-request signal • Only one such transition is seen for every request • Edge-triggered request lines

Interrupt Service • Assuming that interrupts are enabled • Interrupt Service • The device raises an interrupt request (INTR) • The processor interrupts the program currently being executed • Interrupts are disabled • Device is informed that its request has been recognized; in response, it deactivates the interrupt-request signal • Action requested by the interrupt is performed by the service routine (ISR) • Execution of the interrupted program is resumed

Handling Multiple Devices • How can the processor recognize the device requesting the interrupt? • How can a processor obtain the starting address of the appropriate routine (ISR)? • Should a device be allowed to interrupt the processor while another interrupt is being serviced? • How should two or more simultaneous interrupt requests be handled?

Device Identification • Consider the case in which an external device requests an interrupt by activating an interrupt-request line that is common to all the devices. • It is customary to use the complemented form, /INTR, to name the common interrupt request signal because it is active when the signal is low • When the common request line is active, additional information is needed to identify the particular device • The requested information is provided in the status registers of the devices

Device Identification • When a device raises an interrupt request (INTR), it sets a bit in its status register (also called IRQ bit) • The processor polls the devices in a predetermined order until it encounters the first device with its IRQ bit set • An appropriate service routine (ISR) is activated • Pros: polling scheme is easy to implement • Cons: interrupt latency longer • time spent interrogating the IRQ bits of all the devices that may not be requesting any service

Vectored Interrupts • A device requesting an interrupt may identify itself directly to the processor • It supplies a device ID code to the processor that is used to locate the starting address of the ISR for the device • The code is typically in the range of 4 to 8 bits, the remainder of the address is fixed • This arrangement implies that each service routine must start at a specified location

Vectored Interrupts (cont.) • The programmer can bypass this restriction by inserting a branch instruction into that location • The content of this location which holds a new PC value is referred to as the interrupt vector • Additional hardware is needed to support vectored interrupts • Coordination is achieved through the interrupt acknowledge (INTA) control signal issued by the processor • As soon as the processor is ready to service the interrupt, it activates INTA • This causes the device to place the device ID (interrupt vector) code on the data lines of the bus and turn off the INTR signal

Example of an Interrupt Vector Table

Resolving Simultaneous Requests • If several devices share one interrupt request line, some other mechanism is needed • When polling is used to identify an interrupting device, the priority is assigned by the order in which devices are polled • The processor polls the devices in a predetermined order until it encounters the first device with its IRQ bit set

Resolving Simultaneous Requests • In Figure 1, the processor can also enable or disable each individual interrupt separately • The processor should have some means on deciding which request is serviced first and which is delayed • In the priority scheme, the processor accepts the request having the highest priority

Prioritization • The hardware for multiple priorities can be implemented easily by using a distinct interrupt request lines and an interrupt acknowledge line for each device • Interrupts received over these lines are sent to a priority arbitration circuit in the processor (called priority encoder) • A request is accepted only if it has a higher priority level than the priority currently assigned to the processor

Interrupt Nesting • I/O devices should be organized in a priority structure • An interrupt request from a high priority device should be accepted while the processor is servicing another request from a low priority device • The priority level of the processor is the priority level of the program it is executing • The processor accepts interrupts only from devices that have higher priority than its own • The processor’s priority is usually encoded in a few bits of the processor status word • It can be changed by a program instruction that writes into the PSR (processor status register) • Instructions that change the priority are privileged • They can only be executed with the processor being running in a supervisor mode • Any attempt to execute a privileged instruction in a user mode will cause a special type of interrupt: exception

Resolving Simultaneous RequestsExample : daisy chain • INTR is common to all devices • INTA is connected in a daisy chain fashion • When several devices issue the interrupt, INTR is activated • The processor responds by setting INTA to 1 • This signal is received by device 1, device 1 passes it to device 2 only if it does not require any service • If device 1 has a pending request, it blocks the INTA signal and proceeds to put its identifying code on the data lines • In the daisy chain arrangement, the device that is electrically closest to the processor has the highest priority • The scheme of Figure 2 requires fewer wires than that of Figure 1

Interrupt Nesting • The scheme of Figure 1 can accept requests for interrupts from some devices but not from others (i.e., can individually enable or disable). • The two schemes may be combined as follows

Controlling Device Requests • It is important to ensure that interrupt requests are generated only by the I/O devices that are being used by a given program • Idle devices must not be allowed to generate interrupt requests • We need to be able to enable and disable interrupts in the interface circuit of individual devices • IE: Interrupt Enable bit in the device’s interface can be set or cleared by the processor • The IE bit can be part of the status register into which the processor can write • If IE=1, the interface circuit generates an interrupt and sets its IRQ bit whenever its SIN or SOUT bit is set • If IE=0, the interface circuit does not generate an interrupt regardless of the status of SIN or SOUT IE IRQ

Example Using Interrupts • Consider a processor that uses the vectored interrupt scheme (i.e, the devices provide its ID used to determine ISR address) • Starting address of the interrupt service routine (ISR) is stored at memory location INTVEC • Interrupts are enabled by setting both interrupt enable bit 2 (IE) in the device and bit 9 in the processor status word (PSW) to 1 • Assume that at some point in the main program, we wish to read an input line from the keyboard and store the characters in successive byte locations starting at location LINE Main Program Move #LINE, PNTR Initialize buffer pointer Clear EOL Clear end of line indicator BitSet #2, CONTROL Enable keyboard interrupts (i.e., let keyboard interrupt) BitSet #9, PSW Set interrupt enable bit in the PSW ….

Interrupt Service Routine Read each character at each interrupt READ MoveMultiple R0-R1, -(SP) Save registers R0 and R1 on stack Move PNTR, R0 Load address pointer MoveByte DATAIN, R1 Get input character and MoveByte R1, (R0)+ store it in the memory Move R0, PNTR Update pointer CompareByte #$0D, R1 Check Carriage Return Branch != 0 RTRN Move #1, EOL Indicate EOL BitClear #2, CONTROL Disable Keyboard interrupts RTRN MoveMultiple (SP)+, R0-R1 Restore registers R0 and R1 Return from interrupt If one line is read, disable interrupt

Exceptions • Many events can cause an interrupt • All these events are called exceptions • So far we looked at an interrupt caused by a request received from an I/O device Recovery from errors • Many computers include a parity check code in the memory to detect errors in the stored data • If an error occurs, the control hardware detects it and informs the processor by raising an interrupt • The processor may also interrupt a program if it detects an unusual condition such as • Illegal Instructions • The OP-code field does not correspond to any legal instruction • Divide by zero • An arithmetic instruction may attempt to divide by zero

Exceptions • The processor suspends the program and starts an exception service routine • This routine takes appropriate action to recover from the error Debugging • The debugger uses exceptions to provide trace mode (or called single step) and breakpoints • When a processor is operating in the trace mode, an exception occurs after every instruction • Breakpoints: the program is interrupted at specific points selected by the user • An instruction called trap or software interrupt is used to specify breakpoints

Privilege Exception • Certain instructions can only be executed when the processor is in the supervisor mode • An attempt to execute a privileged instruction while in the user mode causes a privilege exception • As a result, the processor switches to the supervisor mode and begins executing the appropriate routine in the OS

Use of Interrupts in OS • Application programs request services from the OS using traps (also called software interrupts) • Most processors have several different software interrupts • Each software interrupts has its own vector code • These instructions can be used to call different parts of the OS • SWI #10

Time Use of Interrupts in OS - Multitasking or Multiprocessing • The processor executes several user programs at the same time • Each program runs for a short period of time called a slice • Time slicing is one implementation of multitasking • The period is determined by a timer tick

Timer Tick Interrupt Circuitry

Use of Interrupts in OS - Multitasking or Multiprocessing • A process can be in one of three states: • Running • Runnable: program is ready for execution but is waiting to be selected by the scheduler • Blocked: the program is not ready to resume execution waiting for some event to occur (e.g., ready signal of a line of characters, a block of data from network, or ready signal from another process) Time slice expired Waiting event Chosen Ready

OS Initialization, Services, Scheduler OSINIT: Set interrupt vectors Time slice clock for SCHEDULER Software interrupt forOSSERVICES Keyboard interrupts for IOData Return OSSERVICES: Examine the stack to determine requested operation Call appropriate routine SCHEDULER: Save current context of a blocked process (say A) Select a runnable process Restore saved context of the new process (say B) Return from interrupt

Multitasking (multiprocessing) • The time tick interrupt causes the scheduler to be executed • The starting address of the scheduler routine is stored in the corresponding interrupt vector by the OSINIT routine at the time the operating system is started • The scheduler routine saves all the information relating to the program, say program A, just interrupted • The scheduler selects for execution another program that was blocked earlier (now runnable), say program B, to be resumed • The scheduler restores the contents of PSW, PC and executes a return from interrupt • Program B executes for a time slice • At the end of the time slice, the clock raises an interrupt, and a context switch to another process takes place • Process: a program and any information that describes the current state of execution

I/O Services using OSSERVICES IOINIT Set process status to the ‘Blocked’ state Initialize memory buffer address pointer and counter Call device driver to initialize device and enable interrupts in the device interface Return from subroutine IODATA Poll devices to determine source of interrupt Call appropriate driver If END==1 then set process status runnable Return from interrupt • While I/O operation is in progress the program that requested it cannot continue execution • The IOINIT routine sets the process associated with the program into the blocked state

I/O Routines using Device Driver • Device driver: all software pertaining to a particular device Keyboard driver KBDINIT Enable interrupts Initialize buffer Return from subroutine KBDDATA Check device status If ready, then transfer a character If character=CR, then {set END=1; disable interrupt} else set END=0 Return from interrupt

Lecture 4-1 I/O Organization