1 / 17

4241 Digital Logic Design Finite State Machine Design Procedure Chapter 5: Synchronous Sequential Logic Sections: 5.7

Princess Sumaya University. 4241 - Digital Logic Design. 2 / 17. . . Concept of the State Machine. Computer Hardware = Datapath Control. . RegistersCombinational Functional Units (e.g., ALU)Busses. . FSM generating sequences of control signalsInstructs datapath what to do nex

giza
Télécharger la présentation

4241 Digital Logic Design Finite State Machine Design Procedure Chapter 5: Synchronous Sequential Logic Sections: 5.7

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

    1. 4241 Digital Logic Design Finite State Machine Design Procedure Chapter 5: Synchronous Sequential Logic (Sections: 5.7)

    2. Princess Sumaya University 4241 - Digital Logic Design 2 / 17 Concept of the State Machine

    3. Princess Sumaya University 4241 - Digital Logic Design 3 / 17 Designing Finite State Machines

    4. Princess Sumaya University 4241 - Digital Logic Design 4 / 17 Example: Detect 3 Consecutive 1 inputs

    5. Princess Sumaya University 4241 - Digital Logic Design 5 / 17 State Table for Sequence Detector Sequence of inputs, outputs, and flip flop states in state table Present state indicates current value of flip flops Next state indicates state after next rising clock edge Output is current output value

    6. Princess Sumaya University 4241 - Digital Logic Design 6 / 17 Finding Expressions for Next State and Output Value Create K-map directly from state table (3 columns = 3 K-maps) Minimize K-maps to find SOP representations Separate circuit for each next state and output value

    7. Princess Sumaya University 4241 - Digital Logic Design 7 / 17 Circuit for Consecutive 1s Detector Note location of state flip flops Output value (y) is function of state This is a Moore machine

    8. Princess Sumaya University 4241 - Digital Logic Design 8 / 17 Concept of the State Machine

    9. Princess Sumaya University 4241 - Digital Logic Design 9 / 17 Concept of the State Machine

    10. Princess Sumaya University 4241 - Digital Logic Design 10 / 17

    11. Princess Sumaya University 4241 - Digital Logic Design 11 / 17 Vending Machine FSM

    12. Princess Sumaya University 4241 - Digital Logic Design 12 / 17 Vending Machine FSM

    13. Princess Sumaya University 4241 - Digital Logic Design 13 / 17 Vending Machine FSM

    14. Princess Sumaya University 4241 - Digital Logic Design 14 / 17 Vending Machine FSM

    15. Princess Sumaya University 4241 - Digital Logic Design 15 / 17

    16. Princess Sumaya University 4241 - Digital Logic Design 16 / 17 Homework In this problem, you will design a simple "three clock pulse" timer circuit. In addition to the clock input, the timer has a "Restart" input (R), two "data" outputs (AB) which indicate the count, and one "beeper" output (C). The behavior of the circuit is as follows: Idle Mode - The timer output is AB=11 and the beeper is off (C=0) as long as R=0. If R=1 on any clock edge in this mode, the counter goes into the Restart mode. Restart/Hold Mode - The timer output is AB=00 and the beeper is off (C=0) as long as R=1. If R=0 on any clock edge in this mode, the timer goes into the Counting mode. Counting Mode - Provided that the counter is not restarted (i.e. provided R=0), the timer goes through the following sequence of data and beeper outputs (one full clock pulse each): A B C 0 0 0 0 1 0 1 0 0 1 1 1 and then returns to Idle Mode. If R=1 on any clock edge in this mode, the timer goes into the Restart/Hold mode. You are to use D-flops, AND gates, OR gates, and inverters to design a Moore machine that performs this function. Carry out your solution as follows: How many states does this machine have? Make a list of these states, giving each a label and a verbal description. How many bits are required to specify all states? Name the state bits and assign values to each for every state. Construct a complete state table for this machine, including all inputs, outputs, and states. Include any don't-care conditions. Construct a state diagram for this machine. How many signals must be generated by combinational logic for this machine? What are they? Use Karnaugh maps to obtain minimized Boolean expressions for combniational circuits which will generate these signals, and draw a circuit diagram for each circuit. Draw a complete circuit diagram for your state machine, showing all inputs and outputs, flip flops, combinational circuits, and interconnects. You can represent each of your combinational circuits from part (d) as a "box" in this diagram, but make sure that the inputs and outputs are clearly labeled on each box.

    17. Princess Sumaya University 4241 - Digital Logic Design 17 / 17 Summary Finite state machines form the basis of many digital systems Designs often start from clear specifications Develop state diagram and state table Optimize using combinational design techniques Mealy or Moore implementations possible

More Related