1 / 28

CSE 140 Lecture 8 Sequential Networks

This lecture covers the various types of memory devices used in Sequential Networks, including latches, flip-flops, SR latches, and D latches. It also discusses implementation techniques and characteristic expressions.

gjansen
Télécharger la présentation

CSE 140 Lecture 8 Sequential Networks

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CSE 140 Lecture 8Sequential Networks Professor CK Cheng CSE Dept. UC San Diego

  2. Part II. Sequential Networks (Ch. 3) Memory / Time steps si xi yi yi=fi(St,X) sit+1=gi(St,X) Clock Memory: Flip flops Specification: Finite State Machines Implementation: Excitation Tables

  3. Memory Devices • Memory Storage • Latches • Flip-Flops • SR, D, T, JK • State Tables • Characteristic Expressions

  4. Memory Storage: Capacitive Loads • Fundamental building block of other state elements • Two outputs: Q, Q • No inputs

  5. Capacitive Loads • Consider the two possible cases: • Q = 0: then Q’ = 1 and Q = 0 (consistent) • Q = 1: then Q’ = 0 and Q = 1 (consistent) • Bistable circuit stores 1 bit of state in the state variable, Q (or Q’ ) • But there are no inputs to control the state

  6. SR (Set/Reset) Latch • SR Latch • Consider the four possible cases: • S = 1, R = 0 • S = 0, R = 1 • S = 0, R = 0 • S = 1, R = 1

  7. SR Latch Analysis • S = 1, R = 0: then Q = 1 and Q = 0 • S = 0, R = 1: then Q = 0 and Q = 1

  8. SR Latch Analysis • S = 1, R = 0: then Q = 1 and Q = 0 • S = 0, R = 1: then Q = 0 and Q = 1

  9. SR Latch Analysis • S = 0, R = 0: then Q = Qprev • S = 1, R = 1: then Q = 0 and Q = 0

  10. y S y = (S+Q)’ Q Q = (R+y)’ R

  11. Flip-flop Components SR F-F (Set-Reset) y S R Q Inputs: S, R State: (Q, y)

  12. Id Q y S R Q* y Q** y** Q*** y*** 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 0 1 0 1 2 0 0 1 0 1 0 1 0 1 0 3 0 0 1 1 0 0 0 0 0 0 4 0 1 0 0 0 1 0 1 0 1 5 0 1 0 1 0 1 0 1 0 1 6 0 1 1 0 0 0 1 0 1 0 7 0 1 1 1 0 0 0 0 0 0 8 1 0 0 0 1 0 1 0 1 0 9 1 0 0 1 0 0 0 1 0 1 10 1 0 1 0 1 0 1 0 1 0 11 1 0 1 1 0 0 0 0 0 0 12 1 1 0 0 0 0 1 1 0 0 13 1 1 0 1 0 0 0 1 0 1 14 1 1 1 0 0 0 1 0 1 0 15 1 1 1 1 0 0 0 0 0 0 State Q y SR Transition State Diagram 00 01 10 00 10 10 01 10 01 11 10 01 11 10 SR 00 11 01 00 11 00 11

  13. CASES: SR=01, (Q,y) = (0,1) SR=10, (Q,y) = (1,0) SR=11, (Q,y) = (0,0) SR = 00 => if (Q,y) = (0,0) or (1,1), the output keeps changing Solutions: 1) SR = (0,0), or 2) SR = (1,1). State table SR inputs 00 01 10 11 PS 0 0 0 1 - 1 1 0 1 - Characteristic Expression Q(t+1) = S(t)+R’(t)Q(t) Q(t) Q(t+1) NS (next state)

  14. SR Latch Analysis • S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!) • S = 1, R = 1: then Q = 0 and Q = 0 (invalid state:Q ≠ NOT Q)

  15. SR Latch Symbol • SR stands for Set/Reset Latch • Stores one bit of state (Q) • Control what value is being stored with S, R inputs • Set: Make the output 1 (S = 1, R = 0, Q = 1) • Reset: Make the output 0 (S = 0, R = 1, Q = 0) • Must do something to avoid • invalid state (when S = R = 1)

  16. D Latch • Two inputs: CLK, D • CLK: controls when the output changes • D (the data input): controls what the output changes to • Function • When CLK = 1, D passes through to Q (the latch is transparent) • When CLK = 0, Q holds its previous value (the latch is opaque) • Avoids invalid case when Q ≠ NOT Q

  17. D Latch Internal Circuit

  18. D Latch Internal Circuit

  19. D Flip-Flop • Two inputs: CLK, D • Function • The flip-flop “samples” D on the rising edge of CLK • When CLK rises from 0 to 1, D passes through to Q • Otherwise, Q holds its previous value • Q changes only on the rising edge of CLK • A flip-flop is called an edge-triggered device because it is activated on the clock edge

  20. D Flip-Flop Internal Circuit • Two back-to-back latches (L1 and L2) controlled by complementary clocks • When CLK = 0 • L1 is transparent, L2 is opaque • D passes through to N1 • When CLK = 1 • L2 is transparent, L1 is opaque • N1 passes through to Q • Thus, on the edge of the clock (when CLK rises from 0 1) • D passes through to Q

  21. D Flip-Flop vs. D Latch

  22. D Flip-Flop vs. D Latch

  23. Latch and Flip-flops (two latches) Latch can be considered as a door CLK = 0, door is shut CLK = 1, door is unlocked A flip-flop is a two door entrance CLK = 1 CLK = 0 CLK = 1

  24. D Flip-Flop (Delay) Id D Q(t) Q(t+1) 0 0 0 0 1 0 1 0 2 1 0 1 3 1 1 1 Q D CLK Q’ State table Characteristic Expression Q(t+1) = D(t) D PS 0 1 0 0 1 1 0 1 NS= Q(t+1)

  25. JK F-F State table Q J JK 00 01 10 11 PS CLK 0 0 0 1 ? 1 1 0 1 ? Q’ K Q(t+1)

  26. JK F-F State table Q J JK 00 01 10 11 PS CLK 0 0 0 1 1 1 1 0 1 0 Q’ K Q(t+1) Characteristic Expression Q(t+1) = Q(t)K’(t)+Q’(t)J(t)

  27. T Flip-Flop (Toggle) State table Q T T PS 0 1 CLK 0 0 1 1 1 0 Q’ Q(t+1) Characteristic Expression Q(t+1) = Q’(t)T(t) + Q(t)T’(t)

  28. Using a JK F-F to implement a D and T F-F Q Q’ D J K CLK D flip flop Q Q’ T J K CLK T flip flop

More Related