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Presenter: Chien-Chih Chen

National Sun Yat-sen University Embedded System Laboratory Effective Software Self-Test Methodology for Processor Cores. Presenter: Chien-Chih Chen. N. Kranitis , A. Paschalis, D. Gizopoulos , Y. Zorian Design , Automation and Test in Europe, 2002. Abstract.

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Presenter: Chien-Chih Chen

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  1. National Sun Yat-sen University Embedded System LaboratoryEffective Software Self-Test Methodology for Processor Cores Presenter: Chien-Chih Chen N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian Design, Automation and Test in Europe, 2002

  2. Abstract Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning technique for sharing the testing task of complex Systems-on-Chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. We introduce an efficient methodology for processor cores self-testing which requires knowledge of their instruction set and Register Transfer (RT) level description. Compared with functional testing methodologies proposed in the past, our methodology is more efficient in terms of fault coverage, test code size and test application time. Compared with recent software based structural testing methodologies for processor cores, our methodology is superior in terms of test development effort and has significantly smaller code size and memory requirements, while virtually the same fault coverage is achieved with an order of magnitude smaller test application time.

  3. Related Works Software-based self-test SBST for nonintrusive microprocessor test [4] – [8] Hardware-based logic BIST techniques for microprocessor test [2] – [4] Software routines for generating self-test sequence [13] Hardware machines for generating self-test sequence [9] – [12] SBST BIST

  4. What’s the Problem ? • Pseudorandom software self-test Large self-test code, large memory requirement and excessive test application time • deterministic software self-test with gate level ATPG * test patterns no have inherent regularity * difficult to base on small loops of instructions & compact test routines • ATPG: Automatic Test Pattern Generation

  5. Self-Test Methodology in [4] Include seed, configuration, patterns number Pseudorandom test patterns Self-test signature Test response Response signature Test application program Test response analysis program On-chip test generation program Find instructions for applying the components tests Expand by Software-emulated LFSR

  6. LFSR • LFSR: Linear Feedback Shift Register • http://en.wikipedia.org/wiki/Linear_feedback_shift_register

  7. Proposed Self-Test Methodology • Self-test routines based on ISA and RTL description • Testability of processor components Depends on the controllability input & observability output • Self-test program development Step 1: information extraction Step 2: instruction selection Step 3: operand selection

  8. Self-Test Program Development • The purpose of information extraction 1. Mapping component operations to processor instruction 2. sorting the instructions according to controllability and obervabilitycharacteristics • Criterion of instruction selection in Ic,o (1) discard instructions which do not propagate the operation O result to register (2) smaller instruction sequence for more easily observable (3) smaller instruction sequence to generate a specific test pattern for input of component C

  9. Self-Test Program Development (Cont.) • Operand selection for high structure fault coverage self-test routines based on deterministic test sets providing a test code library ([9] – [13]) for( each component C ) { for( each operation O belong to C ) { (1) determine Ic,o (2) select I which belongs to Ic,o by using controllability and observability criteria (3) using I to apply deterministic data patterns a C data inputs } if fault coverage ≥ target, exit }

  10. Experimental Results • Parwan: 8-bit CPU, 12-bit address bus, 24 instructions • Synthesized design contains 1300 2-input NAND gates • VHDL simulation: ModelSim • Fault simulation: FlexTest

  11. Test Evaluation Framework Test program RTL description Gate level netlist Assembler VHDL test bench VHDL simulation Capture Processor inputs Fault simulation Fault coverage

  12. Test Program statistics • Memory requirements superiority test program size, data memory for test response storage • Less test time

  13. Fault coverage results • Similar fault coverage

  14. Conclusions • High fault coverage with no hardware overhead and performance degradation • Much less computational effort with deterministic data patterns for every component operation • The superiority in test program size, memory requirements and test application time

  15. Comments • Clear software test methodology based on processor modules • The test concept based on less test program size and less test time • The importance using deterministic self-test routines for effective fault coverage and test time • The concept of coverage definition

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