EE 5340 Semiconductor Device Theory Lecture 07 – Spring 2011

1. EE 5340Semiconductor Device TheoryLecture 07 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

2. Second Assignment • Submit a signed copy of the document posted at www.uta.edu/ee/COE%20Ethics%20Statement%20Fall%2007.pdf

3. Test 1 – Tuesday 22Feb11 • 11 AM Room 129 ERB • Covering Lectures 1 through 9 • Open book - 1 legal text or ref., only. • You may write notes in your book. • Calculator allowed • A cover sheet will be included with full instructions. For examples see http://www.uta.edu/ronc/5340/tests/.

4. Diffusion ofcarriers • In a gradient of electrons or holes, p and n are not zero • Diffusion current,`J =`Jp +`Jn (note Dp and Dn are diffusion coefficients)

5. Diffusion ofcarriers (cont.) • Note (p)x has the magnitude of dp/dx and points in the direction of increasing p (uphill) • The diffusion current points in the direction of decreasing p or n (downhill) and hence the - sign in the definition of`Jp and the + sign in the definition of`Jn

6. Diffusion ofCarriers (cont.)

7. Current densitycomponents

8. Total currentdensity

9. Doping gradient induced E-field • If N = Nd-Na = N(x), then so is Ef-Efi • Define f = (Ef-Efi)/q = (kT/q)ln(no/ni) • For equilibrium, Efi = constant, but • for dN/dx not equal to zero, • Ex = -df/dx =- [d(Ef-Efi)/dx](kT/q) = -(kT/q) d[ln(no/ni)]/dx = -(kT/q) (1/no)[dno/dx] = -(kT/q) (1/N)[dN/dx], N > 0

10. Induced E-field(continued) • Let Vt = kT/q, then since • nopo = ni2 gives no/ni = ni/po • Ex = - Vt d[ln(no/ni)]/dx = - Vt d[ln(ni/po)]/dx = - Vt d[ln(ni/|N|)]/dx, N = -Na < 0 • Ex = - Vt (-1/po)dpo/dx = Vt(1/po)dpo/dx = Vt(1/Na)dNa/dx

11. The Einsteinrelationship • For Ex = - Vt (1/no)dno/dx, and • Jn,x = nqmnEx + qDn(dn/dx)= 0 • This requires that nqmn[Vt (1/n)dn/dx] = qDn(dn/dx) • Which is satisfied if

12. Silicon Planar Process1 • M&K1 Fig. 2.1 Basic fabrication steps in the silicon planar process: • (a) oxide formation, • (b) oxide removal, • (c) deposition of dopant atoms, • (d) diffusion of dopant atoms into exposed regions of silicon.

13. LOCOS Process1 • 1Fig 2.26 LOCal Oxidation of Silicon (LOCOS). (a) Defined pattern consisting of stress-relief oxide and Si3N4 where further oxidation is not desired, (b) thick oxide layer grown over the bare silicon region, (c) stress-relief oxide and Si3N4 removed by etching, (d) scanning electron micrograph (5000 X) showing LOCOS-processed wafer at (b).

14. Al Interconnects1 • 1Figure 2.33 (p. 104) A thin layer of aluminum can be used to connect various doped regions of a semiconductor device. 1

15. Ion Implantation1 • 1Figure 2.15 (p. 80) In ion implantation, a beam of high-energy ions strikes selected regions of the semiconductor surface, penetrating into these exposed regions.

16. Phosphorous implant Range (M&K1 Figure 2.17) Projected range Rp and its standard devia-tion DRp for implantation of phosphorus into Si, SiO2, Si3N4, and Al [M&K ref 11].

17. Implant andDiffusion Profiles Figure 2.211Complementary-error-function and Gaussian distribu-tions; the vertical axis is normalized to the peak con-centration Cs, while the horizon-tal axis is normal-ized to the char-acteristic length

18. References 1 and M&KDevice Electronics for Integrated Circuits, 2 ed., by Muller and Kamins, Wiley, New York, 1986. See Semiconductor Device Fundamentals, by Pierret, Addison-Wesley, 1996, for another treatment of the m model. 2Physics of Semiconductor Devices, by S. M. Sze, Wiley, New York, 1981. 3 and **Semiconductor Physics & Devices, 2nd ed., by Neamen, Irwin, Chicago, 1997. Fundamentals of Semiconductor Theory and Device Physics, by Shyh Wang, Prentice Hall, 1989.