Overview

1. Overview • Finite State Machines • - Sequential circuits with inputs and outputs • State Diagrams • - An abstraction tool to visualize and analyze sequential circuits • Internal Memory • Random Access Memory (RAM) • Volatile – values lost on power loss • - Static RAM (SRAM) • - Dynamic RAM (DRAM) • Read Only Memory (ROM)

2. 4 1 8 4 30 25 5 20 10 15 Combinational vs. Sequential Logic • There are two types of “combination” locks Combinational: Success depends only onthevalues, not the order in which they are set. Sequential: Success depends onthesequenceof values (e.g, R-13, L-22, R-3).

3. Combinational vs. Sequential Circuits • Combinational Circuit • always gives the same output for a given set of inputs • example: adder always generates sum and carry,regardless of previous inputs • Sequential Circuit • has memory - “stores” information, • output depends on stored information (state) plus input • so a given input might produce different outputs,depending on the stored information

4. State Machine • A type of sequential circuit • Combines combinational logic with storage • “Remembers” state, and changes output (and state) based oninputsandcurrent state State Machine Inputs Outputs Combinational Logic Circuit Storage Elements

5. State • The state of a system is a snapshot of all the relevant elements of the system at the moment the snapshot is taken. • Examples: • The state of a basketball game can be represented bythe scoreboard. (Number of points, time remaining, possession, etc.) • The state of a tic-tac-toe game can be represented bythe placement of X’s and O’s on the board.

6. State of Sequential Lock Our lock example has four different states, labelled A-D:A: The lock isnot open,and no relevant operations have been performed. B: The lock isnot open,and the user has completed the R-13 operation. C: The lock isnot open,and the user has completedR-13, followed by L-22. D: The lock isopen.

7. Finite State Machine • A description of a system with the following components: • A finite number of states • A finite number of external inputs • A finite number of external outputs • An explicit specification of all state transitions • An explicit specification of what determines each external output value • Often described by a state diagram. - The set of all possible states. - Inputs that trigger state transitions. - Outputs associated with each state (or with each transition).

8. State Diagram • Showsstates (e.g. A), actions (e.g. B) that cause atransitionbetween states, and the outputs. Locked Locked Open Locked

9. The Clock • Frequently, a clock circuit triggers transition fromone state to the next. • At the beginning of each clock cycle, the state machine makes a transition, based on the current state and the external inputs (Synchronous). • Not always required. In lock example, the input itself triggers a transition (Asynchronous). “1” “0” One Cycle time

10. Implementing a Finite State Machine • Combinational logic • Determine outputs at each state. • Determine next state. • Storage elements • Maintain state representation. State Machine Inputs Outputs Combinational Logic Circuit Storage Elements Clock

11. Storage • Each D flipflop stores one state bit. • The number of storage elements (flipflops) neededis determined by the number of states(and the representation of each state). • Examples: • Sequential lock • Four states – two bits • Basketball scoreboard • 7 bits for each score digit, 5 bits for minutes, 6 bits for seconds,1 bit for possession arrow, 1 bit for half, …

12. Complete Example – Traffic Sign • Design a “blinking” traffic sign which exhibits this behavior: State 1) No lights on  State 2) 1 & 2 on  State 3) 1, 2, 3, & 4 on  State 4) 1, 2, 3, 4, & 5 on  State 1) No lights on  . . ( -Repeat as long as operate switch is turned on. -The system is in state 1 when the operate switch is off) 3 4 1 5 2 DANGERMOVERIGHT

13. Traffic Sign State Diagram Switch on Switch off State bit S1 State bit S0 Outputs State Transitions occur on each clock cycle.

14. Traffic Sign Truth Tables Outputs (depend only on state: S1S0) Next State: S1’ S0’(depend on state and input) Switch Lights 1 and 2 Lights 3 and 4 Light 5 Whenever In=0, next state is 00.

15. Traffic Sign Combinational Logic Edge Triggered D flipflops

16. Another Example of a State Machine Digital Computer “States”: • Fetch Instruction • Fetch Operand(s) • Execute Operation • Store Result • Check for Interrupt • Go to 1.

17. ComputerMemory

18. Computer Memory Hierarchy

19. Main Memory • Address Space • The number of uniquely addressable memory locations • Addressability • The number of bits stored at an addressable location • Unit of Transfer • The number ofbits transferred in a memory read or write {could be the “addressability” or a multiple of it, i.e. the addressability could be • an 8 bit byte, or • a 32 bit word (4 bytes) }

20. Basic Types of Memory Two basic kinds of RAM (Random Access Memory) • Static RAM (SRAM) • fast, maintains data as long as power applied • Dynamic RAM (DRAM) • slower but denser, bit storage decays – must be periodically refreshed. Refreshing interferes with regularity of execution of instruction stream. Also, non-volatile memories: ROM, PROM, flash, …

21. Memory Map 00 00000000 01 01010101 02 11001010 03 00011001 . . . . FF 11001100 What is the Address Space of this memory? What is the Word Length of this memory? What is the Unit of Transfer of this memory?

22. Memory Organization • What would a 1 word by 1 bit memory look like? • How could data be stored in it? • How could data be read from it? • What would a 1 word by 2 bit memory look like? • How could data be stored in it ? • How could data be read from it ? • What would a 2 word by 1 bit memory look like? • How could data be stored in it ? • How could data be read from it ?

23. 22 x 3 Memory Organization word select word WE input bits address write enable address decoder output bits

24. 22 x 3 Memory – 1 Decoder, 3 Multiplexors

25. 22 x 3 Memory – Read of Word at Address 11

26. Memory Design – 1K x 4 A[09:00]    D[03:00] Addr Block Select 

27. Memory Design – 1K x 8 D[07:04] D[03:00] A[09:00]  A[09:00]    D[07:04]   D[03:00] Addr BlockSelect => Addr Block Select =>

28. Memory Design - 2k x 8 D[07:04] D[03:00] Block 01 Block 00

29. D[07:04] D[03:00] Memory Design - 4k x 8 Block 11 Block 10 Block 01 Block 00