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SARA - S caleable A rchitecture for R ealtime A pplications -

SARA - S caleable A rchitecture for R ealtime A pplications -. llh@idt.mdh.se. The research question is : will it be possible to meet the following objectives if software functions and new functions implements in hardware? Scaleable and Simpler Flexible Observable and Controllable

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SARA - S caleable A rchitecture for R ealtime A pplications -

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  1. SARA - Scaleable Architecture for Realtime Applications - llh@idt.mdh.se

  2. The research question is: will it be possible to meet the following objectives if software functions and new functions implements in hardware? Scaleable and Simpler Flexible Observable and Controllable Efficiency and higher Performance Better Low-Cost/Real-time Performance Value, Fault Tolerance, SARA next generation-Scaleable Architecture for Real-time Applications-

  3. We work only with MIMD architecture We work also with Power PC, VME, PCI bus ....

  4. MIMD löst kopplade

  5. MIMD hårt kopplade

  6. MIMD hårt kopplade med Cache

  7. MIMD hårt och löst kopplade (hybrid)

  8. MIMD hårt och löst kopplade (hybrid) med I/O

  9. Scalability and Simple RAM RAM RAM RAM CPU0 CPU1 CPU2 CPUA GRAM RTUA More performance - no change in software - more processors RAM RAM RAM CPU0 CPU1 CPU2 Next sub system RTUB

  10. Flexibility Different software architectures could use the same hardware architecture. New version - no change in hardware - flexible hardware

  11. Problem: Verifikation!Hur får vi styrbar/öppnare system?Gäller också en processor system

  12. Observable and controllable, Shared Pool of Computer Resources... Important, Important... the key to faster verification and better analyse of RT-system

  13. Observable and controllableRoad Map for ASIC Design # gates pro week ASIC ? Verification Design 1990 1995 2000

  14. Low Hardware and Software Overhead (simplifications), state-of-the-art high performance commercial standard microprocessors, buses etc. Hardware faster then software Efficiency and Higher Performance

  15. ASIC designs Standard Components, IP etc. Standard Software and debuggers System on Chip ...... Cost/realtime performance,

  16. Better Task Memory Manager Better Watchdog functions Better Scheduling algoritms etc. Fault tolerance,

  17. SARA 98-99

  18. SARA 98- status today -

  19. Conclusion and future work

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