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Example using bridge over trouble wrappers : automated interface synthesis

Example using bridge over trouble wrappers : automated interface synthesis. Notation introduction. When the protocol is in a state and a clock tick occurs, the transition whose guard evaluates to true is taken. Guards check : an action is blocking if it has a guard.

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Example using bridge over trouble wrappers : automated interface synthesis

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  1. Example using bridge over trouble wrappers : automated interface synthesis

  2. Notation introduction • When the protocol is in a state and a clock tick occurs, the transition whose guard evaluates to true is taken. • Guards check : an action is blocking if it has a guard. • Presence : c? (c must be 1) • Absence : c# (c must be 0) • Req! : a control signal is issued • Address!y : a data signal is issued with value y • They didn’t tell what is the symble “:” means

  3. Pipeline and handshake (1)

  4. Pipeline and handshake (2)

  5. Pipeline definition P = (Q,S,D,V,A,->,q0,qf) Q : 0,1,2,3,4,5 S : Req, Ack, Rdy D : Address, Data V : internal variable A : actions -> : Q x A x Q state transition relation e.x. (0,A1,3) q0 : 0 qf : 5

  6. Handshake definition P = (Q,S,D,V,A,->,q0,qf) Q : 0,1,2,3 S : SEL,READ,ENABLE D : ADDR,RData V : internal variable A : actions -> : Q x A x Q q0 : 0 qf : 3

  7. Interface definition • Given 2 protocols • P1 = (Q1,S1,D1,V1,A1,->,r0,rf) • P2 = (Q2,S2,D2,V2,A2,->,t0,tf) • A specification f : D1 -> D2 relating their data channels must be provided. • I = (Q,S,D,V,A,->,qo,qf) • Q bt (Qt,Qr) where Qt bt P1, Qr bt P2 • S = S1 union S2 • D = D1 union D2 • V : data buffers there is one buffer for each di and f(di) • A : set containing one action complementary to each of the actions in A1 and A2 • -> : relate the different states in Q as per the algorithm • Q0 = <{r0},{t0}> is the initial control state and qf = <{rf},{tf}> is the final state • In addition, I will have a set of counters X = {xi} with one counter for each pair of data channels.

  8. step1 • A complete description of the control state of the interface and its counters in that state is written as [<R,T>,X] • R is a set of states from P1 • T is a set of states from P2 • X is the status of the counters • valid(S,X) is true if, for every data write operation in a candidate action S, all required data has been read in S.

  9. Algorithm 1 interface synthesis Q = empty set Q is the state space of I PendingStates = {[{r0},{t0},X]} Let [R,T,X] be some state in the set pendingStates While pendingState != empty do for all r bt R, S1 : r –S1->, t bt T, S2 : t-S2->do S1`:=computecomplement(S1) S2`:=computecomplement(S2) if valid(S1’US2’,X) then R`:=computetarget(R,S1) T`:=computetarget(T,S2) X`:=modifycounter(x,S1`US2`) addtransition : [R,T,X] -> [R’,T’,X’] if[R’,T`,X`] nbt QUpendingStates then Add [R`,T`,X`] to pending States end if end if end for Add [R,T,X] to Q and remove from pending States end while Prune()

  10. Problems about the algorithm • ComputeComplement(S1)input : a transitionoutput : another transitionis the function return an opposite arrow with the same variable on it? • Valid(S,X)input : S, transition; X, counteroutput : true if every data required in S is available • Computetarget(source,S) return the set that state in S can reach via X (transition) • ModifyCounters(X,S)if a data is required at the transition, the counter is increase. If a data is sent, the counter is decresed.

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