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Chapter 7

Chapter 7. Flip-Flops, Registers, Counters, and a Simple Processor. Chapter Objectives. In this chapter you will learn about: Logic circuits that can store information Flip-flops, which store a single bit Registers, which store multiple bits

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Chapter 7

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  1. Chapter 7 Flip-Flops, Registers, Counters, and a Simple Processor

  2. Chapter Objectives • In this chapter you will learn about: • Logic circuits that can store information • Flip-flops, which store a single bit • Registers, which store multiple bits • Shift registers, which shift the contents of a register • Counters of various types • VHDL constructs used to implement storage elements • Design of small subsystems • Timing considerations

  3. Alarm turned on when On/Off = 1 Alarm turned off when On/Off = 0 Once triggered, alarm stays on until manually reset The circuit requires a memory element Motivation: Control of an Alarm System Set Sensor ¤ On Off Memory Alarm element Reset

  4. The Basic Latch • Basic latch is a feedback connection of two NOR gates or two NAND gates • It can store one bit of information • It can be set to 1 using the S input and reset to 0 using the R input.

  5. A Simple Memory Element • A feedback loop with even number of inverters • If A = 0, B = 1 or when A = 1, B = 0 • This circuit is not useful due to the lack of a mechanism for changing its state A B

  6. Reset Set Q A Memory Element with NOR Gates

  7. The Gated Latch • Gated latch is a basic latch that includes input gating and a control signal • The latch retains its existing state when the control input is equal to 0 • Its state may be changed when the control signal is equal to 1. In our discussion we referred to the control input as the clock • We consider two types of gated latches: • Gated SR latch uses the S and R inputs to set the latch to 1 or reset it to 0, respectively. • Gated D latch uses the D input to force the latch into a state that has the same logic value as the D input.

  8. Gated S/R Latch

  9. Gated D Latch

  10. t su t h Clk D Q Setup and Hold Times • Setup Time tsu • The minimum time that the input signal must be stable prior to the edge of the clock signal. • Hold Time th • The minimum time that the input signal must be stable after the edge of the clock signal.

  11. Flip-Flops • A flip-flop is a storage element based on the gated latch principle • It can have its output state changed only on the edge of the controlling clock signal

  12. Flip-Flops • We consider two types: • Edge-triggered flip-flop is affected only by the input values present when the active edge of the clock occurs • Master-slave flip-flop is built with two gated latches • The master stage is active during half of the clock cycle, and the slave stage is active during the other half. • The output value of the flip-flop changes on the edge of the clock that activates the transfer into the slave stage.

  13. Master Slave Q Q m s Q Q D D Q D Clk Clk Clock Q Q Q (a) Circuit Clock D Q m Q = Q s (b) Timing diagram Q D Q (c) Graphical symbol Master-Slave D Flip-Flop

  14. Q D Clock Q Graphical symbol A Positive-Edge-Triggered D Flip-Flop

  15. Comparison of Level-Sensitive and Edge-Triggered D Storage Elements

  16. Master-Slave D Flip-Flop with Clear and Preset Preset Q D Q Clear

  17. T Flip-Flop

  18. JK Flip-Flop

  19. Registers and Counters • An n-bit register is a cascade of n flip-flops and can store an n-bit binary data • A counter can count occurrences of events and can generate timing intervals for control purposes

  20. A Simple Shift Register

  21. Parallel-Access Shift Register Performs both as a series-to-parallel and a parallel-to-series converter

  22. A Three-Bit Up-Counter • Q1 is connected to clk, Q2 and Q3 are clocked by Q’ of the preceding stage (hence called asynchronous or ripple counter)

  23. A Three-Bit Down-Counter • Q1 is connected to clk, Q2 and Q3 are clocked by Q of the preceding stage (asynchronous or ripple counter)

  24. Clock cycle Q Q Q 2 1 0 Q changes 1 0 0 0 0 Q changes 2 1 0 0 1 2 0 1 0 3 0 1 1 4 0 0 1 5 1 0 1 6 1 0 1 7 1 1 1 8 0 0 0 Derivation of the Synchronous Up-Counter • Q0 changes with clk, Q2 changes when previous state of Q0 was 1, and Q3 changes when previous state of Q1 and Q0 were 1

  25. A Four-Bit Synchronous Up-Counter

  26. Enable Q Q Q Q T T T T Clock Q Q Q Q Clear Inclusion of Enable and Clear Capability

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