1 / 12

Literature Review – An FPGA Implementation of the Simplex Algorithm

Literature Review – An FPGA Implementation of the Simplex Algorithm. Yuta Toriyama. April 29, 2011. Optimization of a linear objective function, given a set of linear constraints Maximize: Subject to: Ex:. Linear Programming. Simplex Algorithm. 1. Are we optimal? If so, we are done

harveygillam
Télécharger la présentation

Literature Review – An FPGA Implementation of the Simplex Algorithm

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Literature Review – An FPGA Implementation of theSimplex Algorithm Yuta Toriyama April 29, 2011

  2. Optimization of a linear objective function, given a set of linear constraints Maximize: Subject to: Ex: Linear Programming

  3. Simplex Algorithm 1. Are we optimal? If so, we are done 2. Select Entering Basic Variable Choose the nonbasic variable that increases the objective function value the fastest 3. Select Leaving Basic Variable Minimum Ratio Test 4. Update Constraint Equations To reflect the new basic feasible solution 5. Repeat

  4. Simplex Algorithm

  5. Simplex Tableau 1 2 3

  6. Opportunities for Parallelism Intra-Iteration Pivoting operation to update Simplex tableau Subtractions conducted in parallel Selection of entering variable Tree structure to find a minimum Ratio test Tree structure to find a minimum Inter-Iteration Stream in multiple problems through pipeline

  7. Architecture Divided up into stages within the Simplex method Stream in multiple problems through pipeline

  8. FPGA Specs • Virtex 4VFX140 • LUTs = 2 x Slices • Comparable size to FPGA on ROACH (Virtex 5SX95T)

  9. Implementation Results Up to 751 variables & constraints Runs @ ~100MHz (w/ double-rate memory subsystem) Problem size, parallel block size, wordlengths are all parametrized “Consumes between 11% and 84% of the 4VFX140”

  10. Comparison Against Software Max 20x (median 9.8x) speedup over commercial software package (CPLEX) running on 3.4GHz PC w/ 1GB RAM Assumes that software and hardware takes the same number of simplex iterations - bad assumption

  11. Summary • Transformation into standard form LP not considered • Minimizing objective function • Finding initial basic feasible solution • Etc… • Parallelism limits problem size and application space to multiple smaller LPs solved simultaneously • The takeaway - very difficult to implement Simplex algorithm in hardware while taking advantage of potential speedup techniques over software

  12. References Bayliss, S., et. al. “An FPGA Implementation of the Simplex Algorithm,” Field Programmable Technology, IEEE International Conference on, pp.49-56, Dec. 2006. Chinneck, J.W. “Practical Optimization: A Gentle Introduction,” 2010.

More Related