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CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/24/2011 (Course Overview)

CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/24/2011 (Course Overview). Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA. http://class.ece.iastate.edu/cpre583/. Class Introduction.

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CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/24/2011 (Course Overview)

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  1. CPRE 583Reconfigurable ComputingLecture 1: Wed 8/24/2011(Course Overview) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

  2. Class Introduction • Class Survey (by next class, phjones@iastate.edu) • Background (year in school, C programming, VHDL/Verilog, EE/CPRE background, ISU login ID) • What would you like to get from this class • Syllabus • Course Expectations • Reinforce research fundamentals • Asking the right question • VHDL handbook (source Synplicity) • http://www.cs.umbc.edu/portal/help/VHDL/VHDL-Handbook.pdf (quick ref) • VHDL online tutorials • http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html • http://www.vhdl-online.de/tutorial/

  3. What you should learn • Basic objectives and topics covered in this class. • VDHL is NOT a programming language. It is a means to describe hardware.

  4. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) • Basic components of an FPGA (Chapter 1) • Overview of ways in which reconfigurable computing can be integrated into a system (Chapter 2) • Examples of reconfigurable systems (Chapter3) • Managing the reconfiguration of systems? (Chapter 4)

  5. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) opcode {+, -, AND, OR} A X ALU B Behavior VHDL: ALU compnt ALU (A,B,opcode,X) case opcode when => opPlus X <= A + B; when => opSub X <= A – B; when => opAND X <= A and B; when => opOR X <= A or B; end case; end component; Structural VHDL: ALU component ALU (A,B, opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X); end component;

  6. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & • Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) opcode {+, -, AND, OR} A X ALU B opcode {+, -, AND, OR} ALU Structural VHDL: ALU component ALU (A,B, opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X); end component; 2 Xadd addAB 4:1 Mux A Xsub subAB X Xand andAB B Xor orAB

  7. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) • Abstraction that allows • Reasoning about computation • Correctness • Extraction of parallelism • Transformations for optimization • Guarantee Properties FPGA CPU Memory

  8. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) • Abstraction that allows • Reasoning about computation • Correctness • Extraction of parallelism • Transformations for optimization • Guarantee Properties Memory Function 2 Function 1 Function 4 Function 3

  9. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) • Abstraction that allows • Reasoning about computation • Correctness • Extraction of parallelism • Transformations for optimization • Guarantee Properties Function 1 Memory Memory Function 2 Memory Function 5 Function 3 Memory Function 4 Memory

  10. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) • Streaming Applications • Data Parallel Applications • Fix/Floating Point Computations • Evolvable Hardware • Performance Trade-offs

  11. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) X <= A+B; X <= A xor B; X <= A and B; X <= A or B; X X X X A A A A addAB xorAB andAB orAB B B B B A B X A B X A B X A B X 0 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 0 1 2-input Look Up Tables (LUTs) FPGA LUT LUT LUT LUT LUT LUT LUT LUT LUT LUT LUT LUT LUT LUT LUT LUT

  12. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (2 Weeks) • 4. Case Studies (1 Week) X <= A+B; X <= A xor B; X <= A and B; X <= A or B; X X X X A A A A addAB xorAB andAB orAB B B B B A B X A B X A B X A B X 0 0 0 1 1 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 0 1 2-input Look Up Tables (LUTs) FPGA LUT addAB LUT LUT LUT LUT LUT xorAB andAB LUT LUT LUT LUT orAB LUT LUT

  13. Main topics • Agenda • 1. Overview (6 Weeks) • a. Reconfigurable HW • b. VHDL • 2. Computation Models & Architectures • (4 Weeks) • 3. Mapping logic to FPGAs • (3 Weeks) • 4. Case Studies (1 Week) Lectures on interesting uses of FPGAs. Ideally covering topics that the class would like to learn more about. Please give suggestions as the semester progresses.

  14. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks)

  15. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) ML507

  16. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks)

  17. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) FPGA PC Echo.vhd Serial UART

  18. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) FPGA PC Echo.vhd (Modify to capitalize only (a-z)) Serial UART

  19. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) FPGA PC Echo.vhd Ethernet (UDP/IP)

  20. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) FPGA PC Echo.vhd (Modify to count strings (e.g. corn!)) Ethernet (UDP/IP)

  21. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) FPGA Power PC PC Display.c Ethernet (UDP/IP) User Defined Instruction VGA Monitor

  22. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) FPGA Power PC PC Display.c Ethernet (UDP/IP) User Defined Instruction VGA Monitor

  23. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) FPGA Power PC PC Display.c Ethernet (UDP/IP) User Defined Instruction VGA Monitor

  24. Machine Problems (MPs) • Agenda • 1. Platform Introduction • 2. Network String Matching • 3. Image: PPC coprocessor • 4. Final Projects(~6 weeks) • Choose your own topic • Groups of 3-4 (maybe 5 for case by case) • Encouraged to take on aggressive projects

  25. Review Syllabus • Objects • Expectations • Grading breakdown • MP grading policy: (more flexible for Distance Students) • Up to 5% added for early completion (Fri Midnight) • -5% after Fri Midnight • -10% additional after Monday Midnight • -10% additional after Tue Midnight • After Wed Midnight will make a note.

  26. What is Reconfigurable Computing? • Ask wiki: http://en.wikipedia.org/wiki/Reconfigurable_computing • Computing on a medium that is not fixed • Examples: • rDPA (course grain reconfiguration) • FPGA (fine grain reconfiguration) • General Purpose Processor (not really) underlining hardware typical executes a relatively small fixed instruction set.

  27. What are rDPAs? • rDPA: reconfigurable Data Path Array • Function Units with programmable interconnects Example ALU ALU ALU ALU ALU ALU ALU ALU ALU

  28. What are rDPAs? • rDPA: reconfigurable Data Path Array • Function Units with programmable interconnects Example ALU ALU ALU ALU ALU ALU ALU ALU ALU

  29. What are rDPAs? • rDPA: reconfigurable Data Path Array • Function Units with programmable interconnects Example ALU ALU ALU ALU ALU ALU ALU ALU ALU

  30. What are FPGAs? CLB CLB CLB CLB CLB CLB CLB CLB Configurable Logic Block CLB CLB CLB CLB CLB CLB CLB CLB • FPGA: Field Programmable Gate Array • Sea of general purpose logic gates

  31. What are FPGAs? Configurable Logic Block • FPGA: Field Programmable Gate Array • Sea of general purpose logic gates CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB CLB

  32. What are FPGAs? Configurable Logic Block • FPGA: Field Programmable Gate Array • Sea of general purpose logic gates CLB CLB CLB CLB CLB CLB CLB CLB

  33. Some FPGA Details CLB CLB CLB CLB

  34. Some FPGA Details ABCD Z 0000 0001 1110 1111 4 input Look Up Table CLB CLB CLB Z A LUT B C D

  35. Some FPGA Details CLB CLB CLB Z A LUT B C D ABCD Z 0000 0001 1110 1111 0 0 0 1 A Z AND B 4 input Look Up Table C D

  36. Some FPGA Details CLB CLB CLB Z A LUT B C D ABCD Z 0000 0001 1110 1111 0 1 1 1 A Z OR B 4 input Look Up Table C D

  37. Some FPGA Details CLB CLB CLB Z A LUT B C D ABCD Z B X000 X001 X110 X111 0 1 1 1 Z 2:1 Mux C 4 input Look Up Table D

  38. Some FPGA Details CLB CLB CLB Z A LUT B C D

  39. Some FPGA Details CLB CLB Programmable Interconnection Point PIP CLB Z A LUT DFF B C D

  40. Some FPGA Details CLB CLB Programmable Interconnection Point PIP CLB Z A LUT DFF B C D

  41. FPGA Usage Models • Experimental ISA • Experimental Micro • Architectures • Run-time adaptation • Run-time Customization CPU + Specialized HW - Sparc-V8 Leon Partial Reconfiguration System on Chip (SoC) Fast Prototyping Full Reconfiguration Parallel Applications • Image Processing • Computational • Biology • Remote Update • Fault Tolerance

  42. Application Area for Acceleration

  43. Development Platform Overview • ML507 Evaluation Platform User Guide (pgs. 14-16) • http://www.xilinx.com/support/documentation/boards_and_kits/ug347.pdf

  44. Machine Problem 1 (MP1) Short Overview • Assigned Fri (8/27), Due Friday (9/10). • Purpose: Make sure you can run the tools. Very light VHDL coding. • Primary Tasks: • Run the echo circuit without modifications • Run the echo circuit with a modification to convert lower case ASCII characters to upper case. • Distance Students: Test using NX for remotely access xilinx.ece.iastate.edu. You can download the NX client from: • For Windows: http://www.nomachine.com/download-client-windows.php • For Linux: http://www.nomachine.com/download-client-linux.php • For MAC OS: http://www.nomachine.com/download-client-macosx.php • For Solaris: http://www.nomachine.com/download-client-solaris.php

  45. VHDL basics • VHDL: (V)HSIC (H)ardware (D)escription (L)anguage • VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit • It is NOT a programming language!!! • It is a Hardware Description Language (HDL) • Conceptually VERY different form C,C++ • Some links to VHDL tutorials • http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html • http://www.vhdl-online.de/tutorial/ • http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)

  46. Some Key Differences from C • C is inherently sequential (serial), one statement executed at a time • VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

  47. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

  48. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

  49. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

  50. Some Key Differences from C VHDL example C example Initially: A,B,C,X,Y,Z,Ans =1 A = B + C X = Y + Z Ans = A + X A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

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