Encryption / Decryption VHDL Core Midterm Presentation Part A

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל Encryption / Decryption VHDL CoreMidterm Presentation Part A Instructor : MonyOrbach Semester : Winter-Spring 2013 Performed By: Watad Duna, WatadEsam Duration : Year

2. Project’s Goals • Implementing RSA Encryption Decryption Core. • Enhancing encryption and decryption processing time. • Achieving standard safety level

3. RSA Theory - Reminder • Key Generation Algorithm • Generate two large random primes, p and q • Compute n = pq and (phi) φ = (p-1)(q-1) • Choose an integer e, 1<e<phi, such that gcd(e,phi) = 1 • Compute the secret exponent d, 1 < d < phi, such that (e x d) ≡ 1 (mod phi) • The public key is (n, e) and the private key (d, p, q)

4. RSA Theory - Reminder(Cont.) • Encryption Sender A does the following: • Obtains the recipient B's public key (n, e) • Represents message as a positive integer m, 1< m< n • Computes c = me mod n • Sends the c to B

5. RSA Theory - Reminder(Cont.) • Decryption Recipient B does the following: • Uses his private key (n, d) to compute m = cd mod n • Extracts the message from the representative m

6. Mathematical problems • Prime factorization • When the numbers are very large, no efficient, factorization algorithm is known • Primality testing • Finding all the prime numbers smaller than a given number

7. System launching Operations • Choosing constant large prime numbers p,q (512 bits), this will determine n(q x p ) and phi (q-1 x p-1) • Finding set of prime numbers k1 k2 .. Kl , such that each gcd(ki,phi) = 1 • Each y fulfills the condition gcd(y,phi)=1 where y=(ki x kj x …. x kt) • Each y could be used as public key ‘e’ • Finding set of d1,d2… dm which suits e1,e2..em • Each di fulfills the condition (di x ei )= 1 (Mod n)

8. The Design Central Control Unit Write Buffer Read Buffer Demul t iplexer Encrypted File File Reg Enc./Dec. Unit Reg Reg Enc./Dec. Unit Reg Reg Enc./Dec. Unit Reg Cache reg

9. Central Control Unit • The task of this unit is to control and synchronize the different units activities. • Data • Demultiplexer input(which determines the chosen output) • Cache hit/miss • Enable load to reg • Enc./Dec. unit finish • Write the content of the write buffer to File System • Start new computing in Enc./Dec. unit • Indicate that there is an available Enc./Dec unit

10. The Enc./Dec. Unit • Inputs • Block of data (binary number) • e\d which had been selected by the control unit • Integer number n • Control signal – start : indicates that the unit should start a new computing. • Address – contains the data’s address in WriteBuffer • Output • c = (m^e)%n • Control signal – finished : Indicates that the computing was finished • Address – contains the data’s address in WriteBuffer • Useful Mathematical identity : (n1xn2)%m= ((n1%m)x(n2%m))%m

11. The Enc./Dec. Unit – The Algorithm • To calculate c = m^e%n • Represent e by it’s binary base ( e= e1e2e3e4… ek) • c = m%n • For i=2 to i=k • If ei=0 then , C  (C x C) % n • If ei=1 then , C ( ((C x C) %n) x m%n ) %n • Return C. • Example e=149 ( e = 10010101) • i=2 , m^2%n= c (m^1%n x m^1%n ) % n • i=3 , m^4%n= c (m^2%n x m^2%n ) % n • i=4 , m^9%n= c (( (m^4%n x m^4%n ) % n ) x m^1%n) %n • i=5 , m^18%n= c (m^9%n x m^9%n ) % n • i=6 , m^37%n= c (( (m^18%n x m^18%n ) % n ) x m^1%n) %n • i=7 , m^74%n= c (m^37%n x m^37%n ) % n • i=8 , m^149%n= c (( (m^74%n x m^74%n ) % n ) x m^1%n) %n

12. Enc./Dec Unit Design reg Mux M %n X reg Mux control e Address

13. Read Buffer • Inputs • blocks of data taken from the File System. • En signal – indicates that there is an available Enc. / Dec. Unit . • Outputs • An un-encrypted/ decrypted block when need. • Size ( blocks) • Should be larger than number of Enc./Dec. Units = const * M Data Data block block block block block block block ReadBuffer En

14. Write Buffer • Inputs • blocks of data taken from the Enc./Dec. Unit / Cache . • En signal – indicates that the data is ready to write to the File System. • Outputs • An un-encrypted/ decrypted blocs when ready to write to the File System. • Size ( blocks) • Should be larger than number of Enc./Dec. Units = const * M Data En block block block block block block block ReadBuffer Data

15. Cache • While encrypting a file byte by byte many repeats are expected so a cache may be useful . • Inputs • A block of data taken from ReadBuffer. • m blocks of data taken from Enc./Dec. Units output. • Outputs • Hit signal – this signal indicates if the input block is cached . • Encrypted/ Decrypted data ( in case of cache hit )

16. Project(Part a) Goals • Golden Matlab model. • Golden C model ( for debug purposes ). • VHDL RSA Encryption\Decryption Core.

17. Gantt Chart

18. Questions?