Improved Migration-Enhanced Epitaxy for Self-Aligned InGaAs Devices

1. Electronic Materials Conference (EMC), 6-25-2009 Improved Migration-Enhanced Epitaxy for Self-Aligned InGaAs Devices Mark A. Wistey University of California, Santa Barbara Now at University of Notre Dame mwistey@nd.edu P. McIntyre, B. Shin, E. KimStanford University S. BankUniversity of Texas Austin Y.-J. LeeIntel U. Singisetti, G. Burek, A. Baraskar, V. Jain, B. Thibault, A. Nelson, E. Arkun, C. Palmstrøm, J. Cagnon, S. Stemmer, A. Gossard, M. RodwellUniversity of California Santa Barbara Funding: SRC mwistey@nd.edu

2. Outline: Channels for Future CMOS • Motivation for Self-Aligned Regrowth • Facets, Gaps, Arsenic Flux and MEE • Si doping and MEE • Scalable III-V MOSFETs • The Shape of Things to Come Wistey, EMC 2009

3. Device properties • Heat transfer • Contacts • Current blocking Air gap VCSEL, Dave Buell thesis Blanket layers AlGaAs ? GaAs InGaAs • Integration: III-V’s on Si • Heteroepitaxy • Selective area growth • And III-V MOSFETs... GaAs AlGaAs Buried het laser, C-W Hu JECS 2007 GaAs Qi Xinag, ECS 2004, AMD Motivation for Self-Aligned Regrowth W.K. Liu et al., J. Crystal Growth v. 311, p. 1979 (2009) • 3D nanofabrication Wistey, EMC 2009

4. High barrier III-V FET with Self-Aligned Regrowth: Small Raccess Self-aligned High Velocity Channel Small Rc } Ultrathin 5nm doping layer High mobility access regions Gate High-k n+ Regrowth Channel In(Ga)P Etch Stop High doping: 1013 cm-2 avoids source exhaustion 2D injection avoids source starvation Dopants active as-grown Bottom Barrier Motivation for Regrowth: Scalable III-V FETs Classic III-V FET (details vary): { Large Area Contacts Gap Source Drain Gate • Advantages of III-V’s Large Rc Top Barrier or Oxide { Channel • Disadvantages of III-V’s Bottom Barrier Implant: straggle, short channel effects InAlAs Barrier Low doping Wistey, EMC 2009

5. Process Flow Prior to Regrowth Fabrication details: U. Singisetti, PSSC 2009 Rodwell IPRM 2008 Pattern gate metal Selective dry etches SiNx or SiO2 sidewalls Encapsulate gate metals Controlled recess etch (optional) Slow facet planes Not needed for depletion-mode FETs Surface clean UV ozone, 1:10 HCl:water dip & rinse, UHV deox (hydrogen or thermal) Regrowth SiO2, SiNx Metals high-k Channel In(Ga)P etch stop InAlAs barrier InP substrate Wistey, EMC 2009

6. Gate • High growth temperature (>490°C): • Selective/preferential epi on InGaAs • No gaps near gate • Rough far field • High resistance MBE Regrowth: Bad at any Temperature? Source-Drain Regrowth Regrowth: 50nm InGaAs:Si, 5nm InAs:Si. Si=8E19/cm3, 20nm Mo, V/III=35, 0.5 µm/hr. 200nm Gap • Low growth temperature (<400°C): • Smooth in far field • Gap near gate (“shadowing”) • No contact to channel (bad) Gate Source-Drain Regrowth SiO2 Metals high-k Channel Wistey, EMC 2009 SEMs: Uttam Singisetti

7. Gap-free Regrowth by MEE Migration-Enhanced Epitaxy (MEE) conditions: 490-560°C (pyrometer) As flux constant ~ 1x10-6 Torr: V/III~3, not interrupted. 0.5nm InGaAs:Si pulses (3.7 sec), 10-15 sec As soak Wistey, MBE 2008 RHEED: 4x2 ==> 1x2 or 2x4 ==> 4x2 with each pulse. SEM Side View SEM Cross Section Top of gate: amorphous InGaAs SiO2 dummy gate SiO2 dummy gate InGaAs Regrowth InGaAs Regrowth Original Interface SEM: Greg Burek SEM: Uttam Singisetti • Smaller gapCrosshatching—relaxation? • High Si activation (4x1019 cm-3). • Quasi-selective growth Wistey, EMC 2009

8. High Temperature MEE: Smooth & No Gaps 460C 490C Gap 540C 560C Smooth regrowth SiO2 dummy gate No gaps, but faceting next to gates SiO2 dummy gate Note faceting: surface kinetics, not shadowing. In=9.7E-8, Ga=5.1E-8 Torr Wistey, EMC 2009

9. Shen & Nishinaga, JCG 1995 Fast surface diffusion = slow facet growth Slow diffusion = fast growth [111] faster SiO2 [100] • But gap persists [100] faster Shadowing and Facet Competition [111] Good fill next to gate. • Shen JCG 1995 says:Increased As favors [111] growth Slow diffusion = rapid facet growth Fast surface diffusion = slow facet growth SiO2 [100] [111]

10. Gate Changes Local Kinetics 1. Excess In & Ga don’t stick to SiO2 2. Local enrichment of III/V ratio 4. Low-angle planes grow instead SiO2 [100] 3. Increased surface mobility • Diffusion of Group III’s away from gate • Solution: Override local enrichment of Group III’s

11. Lowest arsenic flux → “rising tide fill” • No gaps near gate or SiO2/SiNx • Tunable facet competition Control of Facets by Arsenic Flux SEM of single-wafer growth series varying As flux • InGaAs Experiment: • Vary As flux • InAlAs marker layers • Find best fill near gate Increasing As flux InAlAs markers InGaAs SiO2 5x10-6 2x10-6 Cr 1x10-6 0.5x10-6 W Original Interface Wistey, EMC 2009

12. Scalable InGaAs MOSFETs 300 nm SiO2 Cap SiNx 50 nm Cr 50 nm W Mo Mo 5 nm Al2O3 n++ regrowth InGaAs Channel, NID n++ regrowth 3 nm InGaP Etch Stop, NID 10 nm InAlAs Setback, NID 5 nm InAlAs, Si=8x1019 cm-3 200 nm InAlAs buffer Semi-insulating InP Substrate Oblique view Top view SEM Wistey, EMC 2009

13. Scalable InGaAs MOSFETs 300 nm SiO2 Cap SiNx • Conservative doping design: • [Si] = 4x1013 cm-2 • Bulk n = 1x1013 cm-2 >> Dit • Large setback + high doping = Can’t turn off • High Rsource > 350 Ω-µm 50 nm Cr 50 nm W Mo Mo 5 nm Al2O3 n++ regrowth InGaAs Channel, NID n++ regrowth 3 nm InGaP Etch Stop, NID 10 nm InAlAs Setback, NID 5 nm InAlAs, Si=8x1019 cm-3 200 nm InAlAs buffer Semi-insulating InP Substrate Wistey, EMC 2009

14. Silicon Doping in MEE • Electron concentration nearly constant • Si prefers Group III site even under As-poor conditions • Increased mobility by MEE Si Ga Si Ga Si Ga Si Ga Wistey, EMC 2009

15. Regrown InAs S/D FETs 4.7 nm Al203, 5×1012 cm-2 pulse doping In=9.7E-8, Ga=5.1E-8 Torr top of gate InAsregrowth side of gate Mo S/D metal with N+ InAs underneath • InAs native defects are donors.1 • Reduces surface depletion. • Decreased As flux works for InAs too. • Gallium-free= improved selectivity in regrowth 1 Bhargava et al , APL 1997 SEM: Uttam Singisetti Wistey, EMC 2009

16. InAs Source-Drain Access Resistance* *Wistey et al, NAMBE 2009 4.7 nm Al203, InAs S/D E-FET. TLMs corrected for metal resistance. • Total Ron = 600 Ω-μm ➡ Rs < 300 Ω−μm. • gm << 1/Rs ~ 3.3 mS/μm -- Not source-limited. • InAs contacts no longer limit MOSFET performance. Slide: Uttam Singisetti, DRC 2009 Wistey, EMC 2009

17. The Shape of Things to Come Generalized Self-Aligned Regrowth Designs: Raised Recessed Gate Gate Top Barrier Top Barrier n+ Regrowth Channel Channel Back Barrier Back Barrier Substrate Substrate • Self-aligned regrowth can also be used for: • GaN HEMTs (with Nidhi in Mishra group, EMC 2009) • InGaAs HBTs and HEMTs • Selective III-V on Si — remove gaps • THz and high speed III-V electronics Wistey, EMC 2009

18. Conclusions • Reducing As flux improves filling near gate • Self-aligned regrowth: a roadmap for scalable III-V FETs • Provides III-V’s with a salicide equivalent • Can improve GaN and GaAs FETs too • Silicon doping impervious to MEE technique • InAs regrown contacts improve InGaAs MOSFETs... • Not limited by source resistance @ 1 mA/µm • Comparable to other III-V FETs... but now scalable Wistey, EMC 2009

19. Acknowledgements • Rodwell & Gossard Groups (UCSB): Uttam Singisetti, Greg Burek, Ashish Baraskar, Vibhor Jain... • McIntyre Group (Stanford): Eunji Kim, Byungha Shin, Paul McIntyre • Stemmer Group (UCSB): Joël Cagnon, Susanne Stemmer • Palmstrøm Group (UCSB): Erdem Arkun, Chris Palmstrøm • SRC/GRC funding • UCSB Nanofab: Brian Thibeault, NSF Wistey, EMC 2009