林永隆 (Youn-Long Lin) Department of Computer Science National Tsing Hua University

1. High-Level Synthesis of VLSIs 林永隆(Youn-Long Lin) Department of Computer Science National Tsing Hua University THEDATsing Hua Electronic Design Automation

2. VLSI Design Tools • Design Capturing/Entry • Analysis and Characterization • Synthesis/Optimization • Physical (Floor planning, Placement, Routing) • Logic (FSM, Retiming, Sizing, DFT) • High Level(RTL, Behavioral) • Management

3. Specify and ??? Describe and Synthesis Design Methodology Progress Capture and Simulate

4. Why not Synthesis? Why Synthesis? Productivity Performance Loss Correctness Unsynthesizability Re-Targetability Inertial

5. Structural Behavioral Block Algorithm FSM RTL Boolean Gate X’tor GDSII Placement Y-Chart Dan D Gajski Floorplan Physical

6. Structural Behavioral Block Algorithm FSM RTL Boolean Gate X’tor GDSII Placement Layout Synthesis Floorplan Physical

7. Structural Behavioral Block Algorithm FSM RTL Boolean Gate X’tor GDSII Placement Logic Synthesis Floorplan Physical

8. Structural Behavioral Block Algorithm FSM RTL Boolean Gate X’tor GDSII Placement High-Level Synthesis Floorplan Physical

9. Parsing CDFG Structural RTL Synthesis Transformation High Level Synthesis Behavioral Description

10. What Went Wrong? • Too much emphasis on incremental work on algorithms and point tools • Unrealistic assumption on component capability, architectures, timing, etc • Lack of quality-measurement from the low level • Too much promising on fully automation (silicon compiler??)

11. Essential Issues • Behavioral Specification Languages • Target Architectures • Intermediate Representation • Operation Scheduling • Allocation/Binding • Control Generation

12. Behavioral Specification Languages • Add hardware-specific constructs to existing languages • HardwareC • Popular HDL • Verilog, VHDL • Synthesis-oriented HDL • UDL/I

13. Target Architectures • Bus-based • Multiplexer-based • Register file • Pipelined • RISC, VLIW • Interface Protocol

14. Design Space Exploration Delay Arch I Arch II Arch III Area

15. Interactive FSMDs FSM FSM FSM Data Path Data Path Data Path FSM with Data Path (FSMD)

16. Intermediate Representation * * + Data Flow Graph Control Flow Graph

17. Scheduling (Temporal Binding) • Time & Resource Tradeoff • Time-Constrained • Integer Linear Programming (ILP) • Force-Directed • Resource-Constrained • List Scheduling • Other Heuristics • Simulated Annealing, Tabu Search, ...

18. Operations Functional Units Storage Variables Signals Bus/Wire/Mux Data Transfers Allocation/Binding

19. Variables/Signals RF RF Data Transfer FU FU Operations

20. Micro-Operations for Every Control Step Controller Specification Generation Scheduled CDFG Allocated Datapath

21. HLS Quality Measures • Performance • Area Cost • Power Consumption • Testability • Reusability

22. Hardware Variations • Functional Units • Pipelined, Multi-Cycle, Chained, Multi-Function • Storage • Register, RF, Multi-Ported, RAM, ROM, FIFO, Distributed • Interconnect • Bus, Segmented Bus, Mux, Protocol-Based

23. Functional Unit Variations + + * Step 1 * + + * + Step 2 * - Step 3 Step 4

24. RF RF Segmented Buses Multi-Port Mux Distributed FIFO FU FU Chaining Storage/Interconnect Variations

25. Architectural Pipelining FSM Data Path

26. THEDA’s Work on HLS • ILP-based Scheduling • Bipartite Weighted Matching for Datapath Allocation • Performance-Driven Interconnect Synthesis • Loop Folding & Retiming • Integrating Synthesis and Layout • DSP Core Generation • Book on HLS

27. Integer Linear Programming for Scheduling • Given # Control Steps • ASAP + ALAP ==> Possible Steps for each Operations • Tight Constraints on • Dependency • One Scheduled Step per Op • Resource Usage per Step • Many Extensions

28. Advanced Scheduling for Loop Folding 1 1 2 2 3 3 1 iteration per 3 cycles 1 iteration per 2 cycles

29. Prologue Folded Body Epilogue Loop Folding(cont.) 1 2 3

30. 1 1 2 2 3 3 Retiming and Loop Folding A B C D E F A B C D E F E E C A A B F D C F D B

31. Integrating Layout and Synthesis HDL Description P&R RC Extraction & Delay Calculation HDL Synthesis Soft-Macro Formation Soft-Macro Formation Post-Layout Timing Analysis Block Placement Timing Ok & no more area improvement No Soft-Macro Placement Soft-Macro Placement Module Resynthesis Module Resynthesis Chip Layout

32. HLS Techniques for DSP Code Generation Memory Allocation Address Generation Scheduling

33. Applications of HLS Technology • Code generation for embedded processors • Retargetable compilers for application-specific instruction-set processors (ASIP) • Reconfigurable computing • Advanced features in logic synthesizer

34. System-on-a-Chip Processor Memory Wireless Bridge External Memory Interface USB Bus Master IP UART

35. SOC with PLDs Processor Memory Wireless Bridge External Memory Interface USB Bus Master FPGA FPGA

36. System Houses/ IC Vendors (Fabless) Wafer Foundry Library/ IP Vendors (Chipless) Integrators EDA Vendors Paradigm Shift

37. IP and Synthesis • Authoring IP for Synthesis • Synthesis utilizing IP • Synthesizing IPs Executable Data Sheets

38. Executable Data Sheets More than just the Port Interface IP Wrapper IP

39. Future Directions • Realistic Methodology • Evolutional Transition from Current Practice • Domain Specific • IP-Centric • As both Authoring Aid and Integrator • Software • Co-design and Code Generation

40. IC Value IP EDA Time