Company presentation

1. Company presentation • System-Level Design Solutions • Intellectual Property Cores web:www.intron-innovations.com mailto:info@intron-innovations.com Last update: Jan 08, 2009

2. Agenda • INTRON company brief; • Design services; • Products; • Partners; • Contact information. INTRON Ltd. Company presentation

3. INTRON Company Brief INTRON Ltd is a computer hardware and software research and development company. We design and develop System-Level Design Solutions, IP Cores, and SoCs for IC design industry. INTRON is built of highly qualified team of scientists, engineers and designers. Its members have been instrumental in development of the specialized computers, VLSI sets, microprocessor systems, computer tomographs, and dozens of other technologies over past 25 years. INTRON Ltd is a privately held independent company with 30+ employees. We are founded in 2000 and headquartered in L’viv, Ukraine. For more information about INTRON, please visit our webpage: www.intron-innovations.com. INTRON Ltd. Company presentation

4. INTRON Organization Chart INTRON Ltd. Company presentation

5. Design Services INTRON offers a number of design services tailored to meet customer's requirements. Our services include, but are not limited to following areas: •  Application-Specific Integrated Circuits HDL design, including algorithm•  development, design specification, RTL coding, logic synthesis, design•  verification, and test patterns generation; •  Design of data protection hardware and software components for•  computer and telecommunication systems and networks; •  Design of data protection components for wireless systems; •  Algorithms and hardware and software development for signal and image•  processing; •  Digital communication systems design; •  Development of high-performance multithread multichannel processors; •  Soft-Cores design for high-performance reconfigurable accelerators. To find out more about our design services, feel free to contact us. INTRON Ltd. Company presentation

6. Products System-Level Design Solutions Intellectual Property Cores CHAMELEON – ASIC Design Automatic Generation Environment Data Protection Fast Orthogonal Transformations Inter-Core Communications OSCAR – On-line Synthesis of Computers from an Algorithmic Representation Media Arithmetic and Mathematic Functions INTRON Ltd. Company presentation

7. Products / System-Level Design Solutions CHAMELEON – ASIC Design Automatic Generation Environment General information CHAMELEON – the System-Level Design Solution developed by INTRON – is intended for ASIC design automatic generation from the algorithm described on ANSI C language. The developer, specifying an algorithm of the data processing on ANSI C, gets on return fully debugged and synthesizable VHDL RTL model of the device that implements described algorithm. The architecture of the device is fully optimized for the executed algorithm and maximally uses its ability for paralleling. Obtained VHDL design may be further implemented in FPGA by any FPGA design solution, e.g. Xilinx ISE WebPACK. On current phase of development, the CHAMELEON is optimized for Xilinx Virtex FPGAs, and it is being optimized for Altera's FPGAs. Features • Computer schematic synthesis without human's assistance; • Automatic optimization of the device's architecture for executed algorithm; • Customer can determine device's interface and control its performance and gate count; • Automatic test bench generation; • The software is running under Windows OS. INTRON Ltd. Company presentation

8. Products / Intellectual Property Cores Data Protection IP Cores Our Data Protection IP Cores represent vendor-independent VHDL and Verilog implementations of widely used cryptographic algorithms: DES and Triple DES for encryption, and SHA-1 and MD5 for authentication. We are actually working to expand an available set of these IP Cores with AES IP Cores for symmetric, and RSA IP Cores for asymmetric encryption. Data Encryption Standard IP Cores • Ultra-compact ECB-mode DES IP Core • Ultra-compact CBC-mode DES IP Core • Ultra-compact 64-bit CFB-mode DES IP Core • Extra-fast ECB-mode DES IP Core • Extra-fast CBC-mode DES IP Core • Extra-fast 64-bit CFB-mode DES IP Core • Ultra-compact 64-bit OFB-mode DES IP Core Secure Hash Algorithm IP Cores • Fast Processor Core • SHA-1 IP Core with WISHBONE Slave Interface Triple Data Encryption Standard IP Cores • Ultra-compact ECB-mode Triple DES IP Core • Ultra-compact CBC-mode Triple DES IP Core • Ultra-compact 64-bit CFB-mode Triple DES IP Core • Extra-fast ECB-mode Triple DES IP Core • Extra-fast CBC-mode Triple DES IP Core • Extra-fast 64-bit CFB-mode Triple DES IP Core • Ultra-compact 64-bit OFB-mode Triple DES IP Core Message Digest Algorithm IP Cores • Fast Processor Core • MD5 IP Core with WISHBONE Slave Interface INTRON Ltd. Company presentation

9. Products / Intellectual Property Cores Fast Orthogonal TransformationsIP Cores Our Fast Orthogonal Transformations IP Cores are an outcome of more then 25 years of our engineers' and scientists' work in the realm of Fast Orthogonal Transformation algorithms investigation, development and hardware implementation. During these years our staff patented more then 50 inventions of new structures and hardware implementations of Fast Orthogonal Transformation algorithms. Moreover, we have developed means for automatic generation of FFT and FCT IP Cores. An example for the FFT IP Cores is given below. Features • Any radix-2 length direct or inverse FFT; • Fixed complex I/Os with any width; • Arbitrary width of the internal data and coefficient word; • No external memory required; • Fixed-point arithmetic; • Simple interface and timing; • No dead clock cycles; • Fully pipelined structure, fully synchronous; • Registered Inputs and Outputs; • Full test bench supplied; • Natural order input, binary-inverse output. • General information • The FFT Processor computes the N-point complex direct or inverse FFT. The input (output) data is a vector of N complex values represented as 2’s complement numbers – real and imaginary components of a data sample. The input data stream is represented in natural order, the output – in binary-inverse order. FFT IP Cores generation parameters • FFT size; • FFT external word width; • FFT internal word width; • Transformation type; • Test patterns (optional). INTRON Ltd. Company presentation

10. Products / Intellectual Property Cores Inter-Core CommunicationsIP Cores Our Inter-Core Communications IP Cores are intended to eliminate bottlenecks in the System-on-Chip integration. These IP Cores have been created as sufficient auxiliary components of INTRON SoCs. An example for the Inter-Core Communications IP Cores - Multiple-Block RAM Access Controller IP Coreis given below. Features • Input address bus width – 16bit; • Data bus width – 8bit; • Input request lines number – 5; • External RAM blocks number – 3; • Fixed requests processing time – 6 clock cycles; • Supported RAM size – 16kx8bit; • Requests are processed in order for each requester; • Improves a memory bandwidth; • Vendor independent synthesizable VHDL model, netlist for target device. • General information • INTRON’s Multiblock RAM Access Controller provides a complete memory system for SoC. It connects N=5 requesters to M=3 RAM blocks (16k x 8bits). Each of input requests has an information about RAM block number, address in such block, type of request (read or write) and input data (if request type is write). Controller normally serves all requests during fixed time every clock cycle. Controller overflows when the number of input requests exceeds feasible RAM blocks bandwidth. Numbers of overflow cycles depend on input requests intensity. Experimental result shows, that proposed Controller is more efficient than a Simple Controller. For example, if request intensity is 50%, than the proposed Controller bandwidth is 38% better than bandwidth of the Simple Controller. Our approach allows designing a Controller with different parameters and for different types of external RAM controllers (SRAM, DRAM, etc). INTRON Ltd. Company presentation

11. Products / Intellectual Property Cores MediaIP Cores Our Media IP Cores are intended to be used as embedded components of audio/video systems of consumer electronics like camcorders, cameras, DVD etc. These IP Cores can be implemented as components of larger SoC design as well as standalone ASIC modules. An example for the Media IP Cores - RGB2YUV Color Space Converter IP Coreis given below. Features • Converts digital RGB to digital component video YUV; • Optimized for XC4000XLA and Virtex architecture; • Low CLB count/MIPS ratio; • Supports camcorder video streams; • Up to 56 MHz System clock; • Up to 14 MHz RGB change; • One conversion per 8-clock cycle; • All outputs no rounded; • No external logic needed to handle these conditions; • Low latency; • Fully relationally placed for consistent performance; • Supports Xilinx Foundation Series 2.1i development tools. • Functional description • The RGB to YUV color space converter is designed to perform the following equations: • Y = + KYR*R + KYG*G + KYB*B • U = - KUR*R - KUG*G + KUB*B + C1 • V = + KVR*R - KVG*G - KVB*B + C1 • R, G, B – are 10 bit values; • K – are 12 bit values; • Y, U, V – are 23 bit positive values; • C1 – a constant. • The conversion is complete in 8 clock cycles and both input and output are registered for consistent routing and timing. INTRON Ltd. Company presentation

12. Products / Intellectual Property Cores Arithmetic and Mathematic FunctionsIP Cores Our Arithmetic and Mathematic Functions IP Cores implement widely used arithmetic and mathematic functions, which are time-consuming and sometimes not sufficient to be implemented in software for real-time applications. These IP Cores are intended to be used as components of larger SoCs. Examples for our Arithmetic and Mathematic Functions IP Cores are given below. • IEEE754-Standard Floating-Point Number Divider IP Core • IEEE754-Standard Floating-Point Reciprocal Function IP Core Features • Input data word size - 32 bits (IEEE 754 standard); • Output data word size – 32 bits (IEEE 754 standard); • Pipelined structure, 25 pipeline stages; • Input and output registers; • Vendor independent VHDL model, netlist for targetdevice. INTRON Ltd. Company presentation

13. Partners We encourage You to become our Partner INTRON Ltd. Company presentation

14. Contact us Office address:INTRON Ltd,Kulparkivska Str. 59,Building 42,79015, L’viv,Ukraine. Tel: +38 032 2379572 Tel/Fax: +38 032 2957820 Web: www.intron-innovations.com General e-mail enquiries: info@intron-innovations.com Sales and technical enquiries: sales@intron-innovations.com INTRON Ltd. Company presentation