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Virtual Memory

This virtual memory page provides a simplified memory layout for applications, allowing them to think they own all memory. The solution includes protection between processes and mapping virtual memory to physical memory through a page table. Additionally, a translation lookaside buffer (TLB) and cache are used to improve access times.

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Virtual Memory

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  1. Virtual Memory Page that info back into your memory!

  2. Simplifying Memory for Applications • Applications should see the straightforward memory layout we are familiar with • Applications should think they own all of memory • Solution: We give them a virtual view of memory

  3. Protection between Processes • With a bare system, processes can assigned real physical addresses • Which means that nay program can access any address (even one they don’t own) • Soln: We should send all addresses through mechanism that OS controls

  4. Mapping Virtual Memory (VM) to Physical Memory (PM) • We divide into memory into equal sized chunks (about 4 KiB - 8 KiB)

  5. Mapping Virtual Memory (VM) to Physical Memory (PM) • We divide into memory into equal sized chunks (about 4 KiB - 8 KiB), AKA pages!

  6. Mapping VM to PM Any chunk of VM can be mapped to any chunk of PM (“page”)

  7. One Small Problem... • We don’t know how large main memory is • How does system know which page in VM maps to which one in PM? • Use lookup table (page table) to deal with this

  8. Paged Memory Systems • Processor-generated address can be split into: • A page table contains the physical page number • Points to the base of each physical page • Makes it possible to store pages of program non-contiguously

  9. Address Mapping in Page Tables • Page Table functionality: • Incoming request is Virtual Address and we want Physical ADdress • Physical Offset = Virtual Offset (since page aligned) • We just need to swap the Virtual Page Number (VPN) for Physical Page Number (PPN)

  10. Address Mapping in Page Tables • Page Table Implementation • Use VPN as index into PT • Store PPN and management bits (Valid, Access Rights) • Do NOT store data • Data sits in PM

  11. Page Table Layout

  12. Page Table Layout

  13. Page Table Layout

  14. Page Table Layout

  15. Page Table Layout

  16. Page Table Layout

  17. What goes inside the Page Table? Contains either PPN or an indication that it doesn’t exist in main memory Valid bit: 1 → virtual page is in physical memory 0 → OS needs to fetch page from disk Access Rights: provides protection Read, write, Executable

  18. One Other Problem... • Steps to Retrieve Data • 1. Access page table for access translation (lives in PM) • 2. Access correct physical address • Requires two accesses of physical memory!!!! • Solution: build separate cache for Page Table • Called Translation Lookaside Buffer (TLB) • Stores VPN → PPN Mapping translations

  19. Cache versus TLB

  20. Some more Info on TLB • Usually small, typically 32-128 entries • Access time comparable to that of cache • Usually fully associative (or have high associativity)

  21. Address Translation Using TLB

  22. So how do we get the actual value, now that we have the address? • Up to now, usually we would just go to physical memory (or if we’re lucky, just go to the cache). • But now, our memory values are distributed between physical memory and disk! • Remember the valid bit in the page table entries: • Valid bit: • 1 → virtual page is in physical memory • 0 → OS needs to fetch page from disk • Going to physical memory is faster than going to disk, but more expensive ($$$) than disk • Solution: put currently used memory values in physical memory (smaller amount), and the rest on Disk (everything else) • Sound familiar? It’s caching! • Physical memory is a cache for disk! • If we have to go to disk, then that’s a page fault (like a cache miss). • Only having to go to physical memory is like a cache hit, but doesn’t have a cool name.

  23. Remember caches? Physical memory is a cache for disk! Phys. Memory Cache (shortcut for phys. memory) Phys. Memory address Cache Miss Block not in cache, have to go to memory Check the cache In the same way caches dealt in units of blocks (of N bytes), phys. memory has pages (of M > N bytes) Phys. Memory (shortcut for disk) Phys. Memory address Disk Page Fault Check phys. mem. Page not in memory, have to go to disk

  24. Putting it all together (TLB + Cache + MEM + Disk) Address Translation: Phys. Memory address TLB Miss TLB (shortcut for page table) Page Table Virtual Memory address (translates all virtual addr. in use to pages in phys. addr / disk addr.) Addr. not in TLB, have to go to page table to translate Check the TLB TLB Hit Addr. in TLB, can immediately get phys. Addr. translation Accessing contents/value at address: Phys. Memory (shortcut for disk) Cache (shortcut for phys. memory) Disk Phys. Memory address Cache Miss Value/ Contents Page Fault Block not in cache, have to go to memory Check the cache Page not in memory, have to go to disk Cache Hit Page in phys. memory

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