The Partitioning Decision

1. The Partitioning Decision

2. Introduction to Embedded Systems Partitioning HW and SW • Recall the beginning phase of the embedded lifecycle • A significant effort usually goes into partitioning the “algorithm” between the hardware components and the software components • Critical part of the design because mistakes made here can cause an inferior product to result • Software team usually tasked with picking up the pieces • Today, partitioning is becoming an almost seamless process • Tools can be used to create a generalized algorithmic solution (UML) and then partitioned into software and hardware components

3. Introduction to Embedded Systems Partitioning: The duality of software and hardware • The hardware and software in an embedded system work together to solve a problem ( algorithm ) • The decision about how to partition the software components and the hardware components is usually dictated by speed and cost • Dedicated hardware is fast, inflexible and expensive • Reconfigurable hardware is fast, flexible and more expensive • Software is slower, more flexible and cheaper ERROR HANDLING DATA FORMATTING LASER PRINTER ENGINE ALGORITHM DATA TO BE PRINTED CARBON TONER ON PAPER LASER CONTROL MECHANICAL CONTROL

4. Introduction to Embedded Systems HW/SW – Pro and Con • Hardware solution: PRO • Can be factors of 10X, 100X or greater speed increase • Requires less processor complexity, so overall system is simpler • Less software design time required • Unless hardware bug is catastrophic, workarounds might be doable in software • Hardware solution: CON • Additional HW cost to the bill of materials • Additional circuit complexity (power, board space, RFI) • Large NRE charges (~$100K) • Potentially long development cycle (3 months) • Little or no margin for error • Only 50% of ASIC’s work the first time • IP Royalty charges • Hardware design tools can be very costly ($50K-$100K per seat)

5. Introduction to Embedded Systems HW/SW – Pro and Con • Software solution: PRO • No additional impact on materials costs, power requirements, circuit complexity • Bugs are easily dealt with, even in the field! • Software design tools are relatively inexpensive • Not sensitive to sales volumes • Software solutions: CON • Relative performance versus hardware is generally far inferior • Additional algorithmic requirements forces more processing power • Bigger, faster, processor(s) • More memory • Bigger power supply • RTOS may be necessary (royalties) • More uncertainty in software development schedule • Performance goals may not be achievable in the time available • Larger software development team adds to development costs

6. Introduction to Embedded Systems HW/SW cost analysis example • Assume that we are considering the addition of an ASIC to our embedded system • Assume that the cost of developing the ASIC can be summarized as follows:

7. Introduction to Embedded Systems HW/SW cost analysis example (2) • Development costs for a software solution • Summarizing the total costs

8. Introduction to Embedded Systems HW/SW cost analysis example (3) • Let’s assume that the product is an ink jet printer and that we can judge the possible list price versus features • Question: What partitioning direction should we take? • Risk analysis: • 30% probability that ASIC will require a second pass through foundry • $200,000 + 2 months • Software teams have never come in on schedule • Averaged 3 month overrun for last 4 projects • Consumer Electronics Show is in 4 months

9. Introduction to Embedded Systems Partitioning HW and Software • There has been a revolution in hardware design called Hardware Description Languages (HDL) • Commonly known as Verilog and VHDL • Like C, but includes extensions for real time and other hardware realities • Abstracts the design of hardware away from gates and wires to algorithms and state machines • Hardware design is described in HDL and then compiles to a recipe for the silicon FAB to build the circuit • Called Silicon Compilation • A single HW designer can now develop an IC that required entire teams several years ago • This has led to whole new concept of Systems-on-a-chip, or SOC

10. Introduction to Embedded Systems ASIC - Example of HW/SW Duality • The HW and controlling software for an application specific integrated circuit ( ASIC ) are designed as if they were both software • Hardware source code ( HDL ) compiles to fabrication instructions for a silicon foundry • Software source code ( C, C++, JAVA, Ada, Pascal ) compilers to embedded control code ( firmware ) • The partitioning decisions are engineering choices • Modern ASICs, called FPGA’s can be dynamically reconfigured

11. Introduction to Embedded Systems C1 +5VDC A1 C4 B1 A4 A A2 B4 C B2 A3 B C2 B3 GND C3 Another view of HW/SW Duality 1- LOGICAL AND STATEMENT: C is true if and only if A is true AND B is true 2- C Language Construct: Boolean A, B, C ; C = A&&B ; 3- Gate Level HW Design 7408 Device 4- Verilog Language Construct: reg C ; wire A,B ; assign C = A&B ;

12. Introduction to Embedded Systems Another view of HW/SW Duality(2) 2- C Language Construct: Boolean A, B, C ; C = A&&B ; C Compiler/Assembler/Linker/Loader Algorithm implements the AND function Software Implementation 4- Verilog Language Construct: reg C ; wire A,B ; assign C = A&B ; Verilog Compiler/IC Design Library/IC fabrication Hardware created To implement AND Hardware Implementation

13. Introduction to Embedded Systems ASIC: a System-On-Chip ( SOC ) FIRMWARE Embedded Microprocessor ASIC Commercially available “devices” ( IP ) Analog I/O User designed elements Digital I/O

14. Introduction to Embedded Systems Hardware design at the gate level

15. Introduction to Embedded Systems Hardware design in VHDL

16. Introduction to Embedded Systems New HW/SW design flow Iterate Software SW Process Compile to Object code Design Algorithm Write C/C++ Code Write stub-code to simulate HW Integrate Co-design Phase • Define the IP • Partition IP between • HW and SW Design Algorithm Write HDL Code ( Dialect of C ) Write test vectors Run Simulations Compile to Si foundry database HW Process Re-spin the ASIC The differences between the process of designing hardware (ASIC ) and the process of designing software are disappearing Key Point

17. Introduction to Embedded Systems What if…..? • Suppose it was possible to eliminate the distinction between designing embedded hardware and embedded software • Could focus on the algorithmic solution and let the partitioning be a natural consequence of the design • Many of the barriers to effective development would be eliminated • No more, Throw it over the wall! • Would design hardware and software at a higher level of abstraction • Let’s first define Abstraction Level

18. Introduction to Embedded Systems Abstraction layers ( software ) User Interface ( Command ) Operating System ( RTOS ) Application Software Driver ( Firmware or BIOS ) Physical Hardware

19. Introduction to Embedded Systems Processor plus ASIC System-on-Chip The Future of Embedded Systems Embedded system on a board 0.35 u process technology > 106 gates 0.18 u process technology > 4x106 gates

20. Introduction to Embedded Systems Systems on Slicon ( SOC or SOS ) • Natural evolution of embedded systems is towards higher level of integration • Increased functionality per $ • More flexibility • All HW and SW stays as IP until physical device is fabricated • Size of SOC market was $6B in 1998, $16B in 2002 System-level integration of software and hardware virtual components is the single biggest challenge engineers will face in the next decade. Pioneers in the automotive and digital communications industries are paving the way with their efforts to develop a competency in hardware and software co-design. Electronic system-level design, especially the task of hardware/software design and partitioning, has become the primary cause of schedule delays. -Gary Smith, Principal Analyst, Dataquest

21. Introduction to Embedded Systems UML and Co-design • Two new technologies have emerged that address this desire to focus on the algorithm and not the partition • Unified Modeling Language (UML) • iLogix, ObjecTime, Cadence, CoWare • HW/SW Codesign • Synopsys, Mentor Graphics, VAST • UML products, such as Statemate and Rhapsody (iLogix) and Co-design products, such as Seamless ( Mentor Graphics ) blur the distinction between hardware and software • Output of UML tool is C++ application code and/or VHDL code • Partition decisions are made by which code is generated • Objective: Design the algorithm in an implementation independent way • Let the automatic code generator do the grunt work

22. Introduction to Embedded Systems Unified Modeling Language • UML is a way to represent the finite-state behavior of an embedded system: A finite state machine is an abstract machine that defines a set of conditions of existence ( called “states” ), a set of behaviors or actions performed in each of these states, and a set of events that cause changes in states according to a finite and well-defined rule set. • Consider some examples of a finite state machine • Vending machine • Gas pump • Flight control system

23. Introduction to Embedded Systems Vending machine example of a state machine • UML would attempt to model the state machine behavior of the embedded system. • Automatic Code Generation (ACG) methods could generate HDL or C++ code for the actual design implementation

24. Introduction to Embedded Systems UML State Chart representation uP 1 uP 2 DMA uP 3 uP 4 Actors Shared Memory DMA Transaction T1 T2 TIME T3 Deposit message T4 Interrupt req. Interrupt Ack. T5 T6 Retrieve Message T7 T8 T9 T10 Bus request Bus acknowledge Denotes start or flow of an event. Color tracks thread ID. Denotes the end of event.

25. Introduction to Embedded Systems Codevelopment design flow Iterate Software SW Process • Design Algorithm • Write C/C++ Code • Compile to Object • code • Write stub-code • to simulate HW • System Design • Move partitions • What if…. • Simulate bus loading • Co-verification • Exercise SW • Generate Vectors • Validate Interfaces Co-design Phase Integrate • Define the IP • Partition IP between HW • and SW • Design Algorithm • Write HDL Code • ( Dialect of C ) • Compile to Si • foundry database • Write test vectors • Run Simulations Re-spin the ASIC HW Process The distinctions between the process of designing hardware and the process of designing software are blurring Key Point

26. Introduction to Embedded Systems Typical Embedded System Design Cycle • Debuggers • Compilers • RTOS • Spreadsheets • C Models • Domain - Specific • ESDA Tools • Post-release support tools?? Software Development Architect & Specify Maintenance Integrate & Test Protos Enhancement Hardware Development • In-Circuit Emulators • ROM Monitors • EDA SW Tools • ASIC Emulators

27. Introduction to Embedded Systems HW/SW Co-verification • After a design is partitioned and separate HW and SW development is proceeding, how do you know that you’ll get it right? • Re-spinning an ASIC is costly • Fixing a problem in software will reduce performance • HW/SW Co-verification focuses on validating the correctness of the design across the HW/SW interface

28. Introduction to Embedded Systems Where design time is spent System Specification & Design HW & SW Design/Debug Prototype Debug System Test 31% 37% 20% 12% 51% of Time Source: Dataquest Cost to fix a problem Maintenance and upgrade

29. Introduction to Embedded Systems Virtual prototypes - the big win Integrating software and hardware before the prototypes are built FCS Conventional Design Cycle Software Development Specification Protos Integrate & Test Hardware Development Shortened Design Cycle With HW / SW Co-design Verification Time Savings Software Development Specification Integrate & Test Hardware Development Protos First Customer Shipments (FCS)

30. Introduction to Embedded Systems Incremental HW/SW Integration Specification Early iterations Partition Develop Algorithms HDL Develop Algorithms C or C++ Unit testing - Vectors Unit testing - Stub code Co-verification HW System Simulate “SW team is done” Team builds object code Synthesis/Layout/Fab ASIC Spin Fix it in SW Integration Maintenance & upgrade

31. Introduction to Embedded Systems HDL Simulation • For each clock cycle • Read in state of all input pins • Recalculate the state of all internal nodes • Check for timing errors, race conditions, illegal connections • Output the new state of all output pins • Update the user’s display • Can be a very slow process for complex designs • 10s to 100s of clock cycles per second • Too slow for realtime software co-development • BRIGHT IDEA!: Let software run as fast as it can, independently of the HW simulation • Only slow it down when it needs to access the virtual HW • Create a “wrapper function” that converts software to a form that is compatible with the HW simulator

32. Introduction to Embedded Systems V1 V3 V7 V5 V2 V6 V4 CLK ADDR ( 0..31) 0xFF7F00A6 ADDR_VALID* DATA ( 0..31) 0x4567ABFF DATA_VALID WRITE* Convert bus cycles to vectors int *ptr; ptr = (int *)0xFF7F00A6; *ptr = 0x4567ABFF; Or more obscure C: *(unsigned int* ) 0xFF7F00A6 = 0x4567ABFF; or assembly language: MOVE.L #$4567ABFF,D0 MOVE.L D0,$FF7F00A6 HDL WRAPPER V1, V2, V3, V4, V5, V6, V7 C Converter To HDL Simulator BUS FUNCTIONAL MODEL ADDR = 0xFF7F00A6 DATA = 0x4567ABFF

33. Introduction to Embedded Systems I/O Density: Key metric in determining throughput* I/O Density ( percent ) Software type RTOS 0.1 - 1.0 Application 1.0 - 5.0 Driver 1.0 - 10.0 Diagnostic 10.0 - 15.0 Initialization 10.0 - 25.0 * Courtesy of Mike Stanbro, Synopsys, Inc.

34. Introduction to Embedded Systems m fSW = average number of clock cycles per instruction = ISS or real CPU clock frequency fHW Ttr = transit time from the SW execution environment to the simulator and back = HW simulator clock frequency d = I/o density, ie, average fraction of instructions going to the HW simulation n = average # of ISS or CPU clock cycles per bus cycle Calculating System Throughput The average elapsed time per instruction, Ttp, is given by: Ttp = mfHW ( 1 - d ) + fSWfHWdTtr+fSWnd fHWfSW The average throughput , or number of instructions per second, Ftp, is given by Ftp = 1 /Ttp where,

35. Introduction to Embedded Systems Plotting the results in Excel

36. Introduction to Embedded Systems Design Technologies • Automation: synthesis • Verification: hardware/software co-simulation • Reuse: intellectual property cores • Design process models

37. Introduction to Embedded Systems Introduction • Design task • Define system functionality • Convert functionality to physical implementation while • Satisfying constrained metrics • Optimizing other design metrics • Designing embedded systems is hard • Complex functionality • Millions of possible environment scenarios • Competing, tightly constrained metrics • Productivity gap • As low as 10 lines of code or 100 transistors produced per day

38. Introduction to Embedded Systems Specification Automation Verification Reuse Implementation Improving productivity • Design technologies developed to improve productivity • We focus on technologies advancing hardware/software unified view • Automation • Program replaces manual design • Synthesis • Reuse • Predesigned components • Cores • General-purpose and single-purpose processors on single IC • Verification • Ensuring correctness/completeness of each design step • Hardware/software co-simulation

39. Introduction to Embedded Systems The codesign ladder Sequential program code (e.g., C, VHDL) Behavioral synthesis (1990s) Compilers (1960s,1970s) Register transfers RT synthesis (1980s, 1990s) Assembly instructions Logic equations / FSM's Assemblers, linkers (1950s, 1960s) Logic synthesis (1970s, 1980s) Machine instructions Logic gates Implementation Microprocessor plus program bits VLSI, ASIC, or PLD implementation Automation: synthesis • Early design mostly hardware • Software complexity increased with advent of general-purpose processor • Different techniques for software design and hardware design • Caused division of the two fields • Design tools evolve for higher levels of abstraction • Different rate in each field • Hardware/software design fields rejoining • Both can start from behavioral description in sequential program model • 30 years longer for hardware design to reach this step in the ladder • Many more design dimensions • Optimization critical

40. Introduction to Embedded Systems The codesign ladder Sequential program code (e.g., C, VHDL) Behavioral synthesis (1990s) Compilers (1960s,1970s) Register transfers RT synthesis (1980s, 1990s) Assembly instructions Logic equations / FSM's Assemblers, linkers (1950s, 1960s) Logic synthesis (1970s, 1980s) Machine instructions Logic gates Implementation Microprocessor plus program bits VLSI, ASIC, or PLD implementation Hardware/software parallel evolution • Software design evolution • Machine instructions • Assemblers • convert assembly programs into machine instructions • Compilers • translate sequential programs into assembly • Hardware design evolution • Interconnected logic gates • Logic synthesis • converts logic equations or FSMs into gates • Register-transfer (RT) synthesis • converts FSMDs into FSMs, logic equations, predesigned RT components (registers, adders, etc.) • Behavioral synthesis • converts sequential programs into FSMDs

41. Introduction to Embedded Systems idea idea back-of-the-envelope modeling cost increases opportunities decrease sequential program register-transfers logic implementation implementation (b) (a) Increasing abstraction level • Higher abstraction level focus of hardware/software design evolution • Description smaller/easier to capture • E.g., Line of sequential program code can translate to 1000 gates • Many more possible implementations available • (a) Like flashlight, the higher above the ground, the more ground illuminated • Sequential program designs may differ in performance/transistor count by orders of magnitude • Logic-level designs may differ by only power of 2 • (b) Design process proceeds to lower abstraction level, narrowing in on single implementation

42. Introduction to Embedded Systems Synthesis • Automatically converting system’s behavioral description to a structural implementation • Complex whole formed by parts • Structural implementation must optimize design metrics • More expensive, complex than compilers • Cost = $100s to $10,000s • User controls 100s of synthesis options • Optimization critical • Otherwise could use software • Optimizations different for each user • Run time = hours, days

43. Introduction to Embedded Systems Behavior Structural Processors, memories Sequential programs Registers, FUs, MUXs Register transfers Gates, flip-flops Logic equations/FSM Transistors Transfer functions Cell Layout Modules Chips Boards Physical Gajski’s Y-chart • Each axis represents type of description • Behavioral • Defines outputs as function of inputs • Algorithms but no implementation • Structural • Implements behavior by connecting components with known behavior • Physical • Gives size/locations of components and wires on chip/board • Synthesis converts behavior at given level to structure at same level or lower • E.g., • FSM → gates, flip-flops (same level) • FSM → transistors (lower level) • FSM X registers, FUs (higher level) • FSM X processors, memories (higher level)

44. Introduction to Embedded Systems Logic synthesis • Logic-level behavior to structural implementation • Logic equations and/or FSM to connected gates • Combinational logic synthesis • Two-level minimization (Sum of products/product of sums) • Best possible performance • Longest path = 2 gates (AND gate + OR gate/OR gate + AND gate) • Minimize size • Minimum cover • Minimum cover that is prime • Heuristics • Multilevel minimization • Trade performance for size • Pareto-optimal solution • Heuristics • FSM synthesis • State minimization • State encoding

45. Introduction to Embedded Systems Sum of products F = abc'd' + a'b'cd + a'bcd + ab'cd a b c F d Direct implementation 4 4-input AND gates and 1 4-input OR gate →40 transistors Two-level minimization • Represent logic function as sum of products (or product of sums) • AND gate for each product • OR gate for each sum • Gives best possible performance • At most 2 gate delay • Goal: minimize size • Minimum cover • Minimum # of AND gates (sum of products) • Minimum cover that is prime • Minimum # of inputs to each AND gate (sum of products)

46. Introduction to Embedded Systems Minimum cover • Minimum # of AND gates (sum of products) • Literal: variable or its complement • a or a’, b or b’, etc. • Minterm: product of literals • Each literal appears exactly once • abc’d’, ab’cd, a’bcd, etc. • Implicant: product of literals • Each literal appears no more than once • abc’d’, a’cd, etc. • Covers 1 or more minterms • a’cd covers a’bcd and a’b’cd • Cover: set of implicants that covers all minterms of function • Minimum cover: cover with minimum # of implicants

47. Introduction to Embedded Systems cd ab 00 01 11 10 0 0 1 0 00 0 0 1 0 01 1 0 0 0 11 0 0 1 0 10 cd ab 00 01 11 10 0 0 1 0 00 0 0 1 0 01 1 0 0 0 11 0 0 1 0 10 a b F c d Minimum cover: K-map approach • Karnaugh map (K-map) • 1 represents minterm • Circle represents implicant • Minimum cover • Covering all 1’s with min # of circles • Example: direct vs. min cover • Less gates • 4 vs. 5 • Less transistors • 28 vs. 40 K-map: sum of products K-map: minimum cover Minimum cover F=abc'd' + a'cd + ab'cd Minimum cover implementation 2 4-input AND gate 1 3-input AND gates 1 4 input OR gate →28 transistors

48. Introduction to Embedded Systems K-map: minimum cover that is prime cd ab 00 01 11 10 0 0 1 0 00 0 0 1 0 01 1 0 0 0 11 Minimum cover that is prime 0 0 1 0 10 F=abc'd' + a'cd + b'cd a b F c Implementation d 1 4-input AND gate 2 3-input AND gates 1 4 input OR gate →26 transistors Minimum cover that is prime • Minimum # of inputs to AND gates • Prime implicant • Implicant not covered by any other implicant • Max-sized circle in K-map • Minimum cover that is prime • Covering with min # of prime implicants • Min # of max-sized circles • Example: prime cover vs. min cover • Same # of gates • 4 vs. 4 • Less transistors • 26 vs. 28

49. Introduction to Embedded Systems Minimum cover: heuristics • K-maps give optimal solution every time • Functions with > 6 inputs too complicated • Use computer-based tabular method • Finds all prime implicants • Finds min cover that is prime • Also optimal solution every time • Problem: 2n minterms for n inputs • 32 inputs = 4 billion minterms • Exponential complexity • Heuristic • Solution technique where optimal solution not guaranteed • Hopefully comes close

50. Introduction to Embedded Systems Heuristics: iterative improvement • Start with initial solution • i.e., original logic equation • Repeatedly make modifications toward better solution • Common modifications • Expand • Replace each nonprime implicant with a prime implicant covering it • Delete all implicants covered by new prime implicant • Reduce • Opposite of expand • Reshape • Expands one implicant while reducing another • Maintains total # of implicants • Irredundant • Selects min # of implicants that cover from existing implicants • Synthesis tools differ in modifications used and the order they are used