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MOSCAP Non-idealities

MOSCAP Non-idealities. Effect of oxide charges Poly-Si gate depletion effect V T adjustment HW9. Oxide Charges. Within the oxide: Trapped charge Q ot High-energy electrons and/or holes injected into oxide Mobile charge Q M

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MOSCAP Non-idealities

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  1. MOSCAP Non-idealities • Effect of oxide charges • Poly-Si gate depletion effect • VT adjustment • HW9

  2. Oxide Charges • Within the oxide: • Trapped charge Qot • High-energy electrons and/or holes injected into oxide • Mobile charge QM • Alkali-metal ions, which have sufficient mobility to drift in oxide under an applied electric field • At the interface: • Fixed charge QF • Excess Si (?) • Trapped charge QIT • Dangling bonds

  3. Threshold Voltage Shift (x is defined to be 0 at metal-oxide interface) Fixed charge: Mobile charge: Trapped charge:

  4. Oxide Charge Effect on CV Mobile ion: Trapped charge:

  5. + + + + + + + + - - - - - - - - - Gate Depletion and Inversion Gauss’s Law dictates that Wpoly = eoxEox / qNpoly n+ poly-Si Cpoly Cox N+ p-type Si Inversion layer thickness:

  6. Effective Oxide Capacitance, Coxe

  7. VT Adjustment • A relatively small dose NI(units: ions/cm2) of dopant atoms is implanted into the near-surface region of the semiconductor that shifts the threshold voltage in the desired direction.

  8. The MOSFET Non-idealities • Velocity saturation • Short channel effect • HW11

  9. Velocity Saturation • Velocity saturation limits IDsat in sub-micron MOSFETS • Simple model: • Esat is the electric field at velocity saturation: for e < esat for eesat

  10. MOSFET I-V with Velocity Saturation In the linear region: EE130/230M Spring 2013 Lecture 22, Slide 10

  11. Short- vs. Long-Channel NMOSFET For very short L:

  12. The Short Channel Effect (SCE) i) VT roll-off ii) DIBL ii) Degraded SS

  13. The Short Channel Effect (SCE) iv) Punch-through

  14. Hot carriers and SD structure • The lateral electric field peaks at the drain end of the channel. • High E-field causes: • Damage to oxide interface & bulk (trapped oxide charge  VT shift) • substrate current due to impact ionization: LDD structure:

  15. Current and voltage with Parasitic SD Resistance G RD RS S D • For short-channel MOSFET, IDsat0 VGS– VT, so that •  IDsatis reduced by ~15% in a 0.1 mm MOSFET. • VDsatis increased to VDsat0+IDsat(RS+ RD)

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