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Architecture and Features

Architecture and Features. Agenda. Top-level architecture and attributes Configurable logic block Memory I/O block Three-state buses Clocks and delay-locked loops Power down mode Configuration. Introducing the Spartan-II FPGA.

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Architecture and Features

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  1. Architecture and Features

  2. Agenda • Top-level architecture and attributes • Configurable logic block • Memory • I/O block • Three-state buses • Clocks and delay-locked loops • Power down mode • Configuration

  3. Introducing the Spartan-II FPGA

  4. The Leading Programmable Logic Solution for Consumer Electronics • Plentiful logic and memory resources • 15K to 200K system gates (up to 5,292 logic cells) • Up to 57 Kb block RAM storage • Flexible I/O interfaces • From 86 to 284 I/Os • 16 signal standards • High performance • System frequency as high as 200 MHz

  5. Complete Solution • Low power • Power down mode guarantees minimum power • 2.5-V core supply voltage • Programmable flexibility • Speeds time to market for your product • Lowest cost FPGAs in the industry • 100,000 system gate device for $10 Pricing for 250,000 units, end-2000, slowest speed, cheapest package

  6. Spartan-II Top-level Architecture • Configurable logic blocks • Implement logic here! • I/O blocks • Communicate with other chips • Choose from 16 signal standards • Block RAM • On-chip memory for higher performance

  7. Spartan-II Top-level Architecture (cont’d) • Clocks and delay-locked loops • Synchronize to clock on and off chip • Rich interconnect resources • Three-state internal buses • Power down mode • Lower quiescent power

  8. Spartan-II Family Overview

  9. CLB Slice (Simplified) • 1 CLB holds 2 slices • Each slice contains two sets of the following: • Four-input LUT • Any 4-input logic function • Or 16-bit x 1 RAM • Or 16-bit shift register

  10. CLB Slice (cont’d) • Each slice contains two sets of the following: • Carry & control • Fast arithmetic logic • Multiplier logic • Multiplexer logic • Storage element • Latch or flip-flop • Set and reset • True or inverted inputs • Sync. or async. control

  11. LUT LUT LUT LUT Dedicated Expansion Multiplexers CLB • MUXF5 combines 2 LUTs to form • 4x1 multiplexer • Or any 5-input function • MUXF6 combines 2 slices to form • 8x1 multiplexer • Or any 6-input function Slice MUXF6 MUXF5 Slice MUXF5

  12. Dedicated Multiplier Logic • Highly efficient ‘shift & add’ implementation • For a 16x16 multiplier • 30% reduction in area • 1 less logic level

  13. Look-up Table Shift Registers LUT • Each LUT can be configured as shift register • Serial in, serial out • Dynamically addressable delay up to 16 cycles Q IN D 0 CE CE CLK Q D 1 CE OUT Q D 2 CE CLB Slice Slice LUT LUT Q D 15 CE LUT LUT ADDR[3:0]

  14. Flexible Cycle Delays LUT • Use for programmable clock delay • Cascade for greater cycle delays • Use CLB flip-flops to add depth Q IN D CE CE CLK Q D CE OUT Q D CE CLB Slice Slice LUT LUT Q D CE LUT LUT ADDR[3:0]

  15. DSP Coefficients Small FIFOs Shallow/Wide 16x1 Distributed RAM bytes Memory Bandwidth and Flexibility • Spartan-II on-chip SelectRAM+TM memory Large FIFOs Packet Buffers Video Line Buffers Cache Tag Memory Deep/Wide SDRAM ZBTRAM SSRAM SGRAM 4Kx1 2Kx2 1Kx4 512x8 256x16 Block RAM External RAM kilobytes megabytes 200 MHz Memory Continuum Highest performance FPGA memory system

  16. Block RAM Provides 4K Bits Each • Dual read/write ports, each with: • Independent clock, R/W, and enable • Independently configurable data width from 4Kx1 to 256x16 W R Port A Spartan-II Dual-R/WPort Block RAM Port B Data Flow Spartan-II A to B Yes B to A Yes A to A Yes B to B Yes R W W W R R

  17. Block RAM Timing • Clock-to-output (glitch-free): 2.5 ns typ. • Address/data input setup: 1.0 ns typ. • Lookup table based RAM provides additional small memories (16x1) • Same timing as CLB logic • Both easily initialized at configuration to simulate ROM

  18. I/O Block (Simplified) • Registered input, output, 3-state control • Programmable slew rate, pull-up, pull-down, keeper and input delay

  19. I/O Interface Standards • I/O can be programmed for 16 different signal standards • VCCO controls maximum output swing • VREF sets input, output, three-state control • Different banks can support different standards at the same time • Logic level translation • Boards with mixed standards

  20. IOBs Organized As Independent Banks • As many as eight banks on a device • Package dependent • Each bank can be assigned any of the 16 signal standards

  21. Spartan-II As Center forSignal Translation • Chip to Chip • LVTTL, LVCMOS • Chip to Memory • SSTL2-I, SSTL2-II, SSTL3-I, • SSTL3-II, HSTL-I, HSTL-III, • HSTL-IV, CTT • Chip to Backplane • PCI33-5V, PCI33-3.3V, • GTL, GTL+, AGP SSTL SDRAM HSTL LVTTL LVCMOS CTT SRAM GTL+ Allows support for future standards!

  22. Performance Challenge Met by Spartan-II Speed • Consistently high performance across I/O signal standards

  23. Performance Challenge Met by Spartan-II Speed (cont’d) • Dedicated block RAM equals ASIC performance • Delay-locked loop maximizes internal & external performance

  24. Comparison ofInterface Standards

  25. Vector Based Interconnect 2ns 2ns 2ns 2ns CLB Array High Performance Routing • Hierarchical routing • Singles, hexes, longs • Sparse connections on longer interconnects for high speed • Routing delay depends primarily on distance • Direction independent • Device-size independent • Predictable for early design analysis

  26. Internal Three-state Buses • Two 3-state drivers per CLB • Permits using internal 3-state buses for a “system on a chip” • OR-AND logic implementation in place of 3-state drivers

  27. Internal Three-state Buses (cont’d) • Low power • No danger of contention when multiple BUFTs enabled • No physical pullups or large capacitance to drive • With no drivers enabled, bus is a logic 1

  28. General Clock Support • Four dedicated global low skew buffers • Dedicated input pin (clock distribution only) • 66-MHz PCI with 500-ps maximum skew • Input IOB flip-flop (no data delay): ts = 3 ns / th = 0 ns • Output IOB flip-flop: tco = 6 ns typ. • Additional shared resources (e.g., long lines) • Distribute low-skew/high-fanout signals (10 ns max.) • Four delay-locked loops on each device • Two global buffers associated with each DLL pair • All-digital implementation

  29. Delay-locked Loop Functions • Eliminate clock distribution delay for fast TCO • System synchronization (e.g., clock mirrors) • Phase-shifted clocks • Clock multiplication and division • Clean up clocks with 50/50 duty cycle correction • Clock lock for internal & external synchronization • DLL feedback connected internally or externally • Can synchronize configuration to DLL lock

  30. DLL Macros • Two DLL versions available • Controlled by macro choice • CLKDLL (low frequency) • Input frequency: 25 MHz to 100 MHz • All 6 outputs available • CLK0, CLK90, CLK180, CLK270, CLK2X & CLKDV • CLKDLLHF (high frequency) • Input frequency 60 MHz to 200 MHz • 3 outputs available • CLK0, CLK180 & CLKDV

  31. Improved Clock-to-out Using DLL • Spartan-II clock-to-out delays reduced over 50% Output standard = LVTTL Fast 16mA (OBUF_F_16) Temp=room, Vdd=2.5V, Vcco=3.3V Waveforms: 1: CLKIN 2: DATA OUT (no DLL) 3: DATA OUT (DLL deskewed) Timing w/o DLL w/ DLL r->r r->f r->r r->f 3.6n 3.5n 1.4n 1.4n

  32. Spartan-II DLLs ImproveClock Networks Deskew Clocks on Board DLL1 DLL2 Deskew Clocks on Chip Cascade DLLs Manage up to 4 System Clocks Convert Clock Levels using Select I/O DLL3 DLL4 • Generate • Clocks • multiply • divide • shift Delay locked loops synchronize on-chip and board level clocks

  33. Power-down Mode • Controlled by single power down pin • All inputs blocked, appear low internally • All outputs disabled • All register states preserved • Power-down status pin • Synchronous wake up • 100 uA typical

  34. Configuration Modes There are four ways to program a Spartan-II FPGA

  35. Partial Reconfiguration • Frame by frame reconfiguration supported while device is running • Routing changes affect device operation • Re-initializing a block RAM requires stopping all access in that column • Can dynamically load the required logic at a given time • Minimizes cost further by time-multiplexing the logic resources

  36. Spartan-II Architecture Summary • Delivers all the key requirements for ASIC replacement • 200,000 gates • 200 MHz • Flexible I/O interfaces • On-chip distributed and block RAM • Clock management • Low power • Complete development system support

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