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Characterization Presentation Spring 2010 ASIC Tester Abo -Raya Dia - 4 th year student

Characterization Presentation Spring 2010 ASIC Tester Abo -Raya Dia - 4 th year student Damouny Samer - 4 th year student. Supervised by: Ina Rivkin. Overview :. Objective: testing the ASIC’s functional correctness

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Characterization Presentation Spring 2010 ASIC Tester Abo -Raya Dia - 4 th year student

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  1. Characterization Presentation Spring 2010 ASIC Tester Abo-Raya Dia- 4th year student DamounySamer- 4th year student Supervised by: Ina Rivkin

  2. Overview : • Objective: testing the ASIC’s functional correctness • Comparing the provider’s input with the expected outputs • Providing options for viewing and analyzing the results

  3. PC User Interface FPGA Project Description : ASIC tester DUT PCIe NOGA StarII Adaptive board GiDELPROCe

  4. So Far

  5. Technical specifications : • The tester supports up to 96 inputs/outputs and up to • 48 bi-directional pins. • Samples I/O signals up to 100 MHz rate. • Independent voltage suppliers: -10 v- 10v. • 1G memory for each input and output vectors . • Two clk pins .

  6. Hardware: • Sending the vectors from DDR A to FIFO IN (working with the high Freq. ) • Transferring the vectors to the DUT via the voltage translators on the PSDB • (working with the DUT Freq. ) • Sampling the DUT outputs and saving them in DDR B

  7. Software: • Configuring the ports • Defining the ASIC’s work conditions (clocks & voltage level ) • Sending the input vectors to the DDR • Comparing the outputs with the expected outputs . Configuration mode screen Debug mode screen

  8. New Features

  9. Hardware Changes : The Loop command : Send the vectors between lines a & b N times . Requirements: Loop nesting :2. Writing the output vectors to the output file in a cyclic way. The need to match between the inputs & outputs .

  10. 2. Embedded Logic Analyzer : Allow the user to see the signals between the FPGA & the DUT, when a trigger occured. Requirements : a. In order to see the signals , the User should launch Altera Signal Tap , with no need to compile the design . b. To raise the trigger when we recognize a combination of the input Data .

  11. Software Changes : 3. Waves Library: Creating an input vectors based on waves library , e.g. : counter (increment/decrement), pulse, random , const. value ,compound clk (clk edges time ,frequency , Duty cycle ) . Counter : start from a , each clock cycle increment or decrement the vector by x , till you reach b .

  12. 4. Sampling frequency: Allow the user to sample the outputs with a higher frequency than the DUT. 5. Graph : A graph for all the output files, when each file was with another frequency .

  13. Summary: The new debug mode Logic Analyzer Loop Load wave Sampling Freq. Summary Graph

  14. Gant chart :

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