General Machine Timing System @ FAIR

1. General Machine Timing System @ FAIR Just a few slides…. Dietrich Beck - BEL

2. Timing Systems @ FAIR Bunch phase Timing System (BuTiS) • invest € 15k per receiver station • ps precision (100ps/km accuracy) • distribution of • clocks!!! • NO time-stamps at FAIR • NO timing-events • HF group • one global BuTiS center Talk P. Moritz, FAIR Technikforum General Machine Timing System • based on White Rabbit • fairly cheap: € 800,- SPEC board • sub-ns synchronization • distribution of • (clock) • time-stamps • timing-events • BEL group • one global timing master • clock derived from BuTiS Talk T. Fleck, FAIR Technikforum Remark: If you are interested time-stamps, you need White Rabbit. If you are interested in the most accurate clocks, you need BuTiS. If you are interested in both, you need both. Dietrich Beck - BEL

3. General Machine Timing System (GMT) @ FAIR parallel execution of beam production chains cycles: 20ms to hours trigger and sync. equipment actions 1 µs precision in 99% of all cases few ns precision for kickers (few ps for rf-systems: BuTiS) many rings > 2000 devices connected to timing system large distances robustness: lose at most one message per year Dietrich Beck - BEL

4. GMT – Idea set value (schedule) LSA timing events set values (ramp) • SM transmits set values • DM executes schedule by broadcasting timing events • FTRN schedule actions • timely execution of action (here: send IRQ to CPU) • Generate ramp via equipment interface Dietrich Beck - BEL

5. GMT – Interfaces FrEC Dietrich Beck - BEL

6. GMT – Data Master SIS18 SIS100 HESR UNILAC beamline Dietrich Beck - BEL

7. SM generates set value for DM: schedule and alternatives (decision tree, domain specific language) SM sends set value to FESA class of DM FESA class uses a library for on-the-fly source-code generation for soft-CPUs cross-compilation of soft-CPU codes uploading codes to soft-CPUs codes specific to schedule rather simple code Settings Management – Data Master Dietrich Beck - BEL

8. Simple Machine Specific Soft-CPU Code SIS100: while (state == PRODUCTION) { /* one cycle: BPC1 */ if (IL(BPC1) != OK) cycle1_planB(); else { waitsync(BPC1, INJ_SIS100, timeout); cycle1(); } /* one cycle: BPC2 */ if (IL(BPC2) != OK) cycle2_planB(); else { waitsync(BPC2, INJ_SIS100, timeout); cycle2(); } /* repeat cycle: BPC2 */ if (IL(BPC2) != OK) cycle2_planB(); else { waitsync(BPC2, INJ_SIS100, timeout); cycle2(); } } not shown: • beam processes • error handling • beam request on/off • IL check during cycle execution Dietrich Beck - BEL

9. 2012 2014 2017 no loosely coupled machines 1 timing master 2 switch layers at TM 4 cables to each building then: distribution to floors then: distribution to rooms 70 m redundant links between switches optical or copper links to nodes 2000-3000 nodes 5 layers of switches (18 ports) in total Dietrich Beck - BEL

10. Timing-Events – synchronizing actions Info-Telegrams – transmission of (float)-values, e.g. beam-intensity “Action-Events” Commit – switching between FrEC registers containing different set values. Post-Mortem – “freeze” or “unfreeze” ring buffers in FrECs Reset – reset a crashed FrEC Rollback – “undo”? Timing Master to Nodes – Message Types Dietrich Beck - BEL

11. Forbidden! … except a few specific cases… Fast beam request from local areas (experiments…) via dedicated local interface units managed by BEL Bunch-to-bucket transfer (transfer between ring machines) Nodes to Timing Master – Message Types Dietrich Beck - BEL

12. Network: Talk by Maciej and Cesar Nodes: In-Kind contribution by Slovenia Network and Nodes Dietrich Beck - BEL

13. Finalize “WR Starter Kit” Timing System v0.0 – experimental, but 24/7 (2012) Timing System for p-Linac test in Saclay (Beginning 2013) Test: replacing MIL-timing of SIS18 + ESR ( 2014) … The Plan Dietrich Beck - BEL