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Latch & Register Inference

Latch & Register Inference. Latch Inference. In non-clocked processes, incompletely specified if and case statements cause synthesizers to infer latches for the variables and signals being assigned. --data_out is a latch Process(somesignal) Begin if (somesignal=‘1’) then

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Latch & Register Inference

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  1. Latch & Register Inference DSD,USIT,GGSIPU

  2. Latch Inference • In non-clocked processes, incompletely specified if and case statements cause synthesizers to infer latches for the variables and signals being assigned. DSD,USIT,GGSIPU

  3. --data_out is a latch Process(somesignal) Begin if (somesignal=‘1’) then data_out<= data_in; end if; End process; Process (somesignal) Begin case somesignal is when ‘0’ => data_out<= data_in; End case; End process; Example A latch is inferred for the signal data_out because is not assigned under all possible conditions. If the tested condition fails then data_out must hold the previous value. DSD,USIT,GGSIPU

  4. Definition • Basic Latch is a feedback connection of two NOR gates or two NAND gates, which can store one bit of information. It can be set to 1 using the S input and reset to 0 using the R input. • Gated Latch is a basic latch that includes input gating and a control input signal. The latch retains its existing state when the control input equals to 0. Its state may be changed when the control signal is equal to 1. DSD,USIT,GGSIPU

  5. Definition (cont..) • Flip Flop: A flip flop is a storage element based on the gated latch principle, which can have its output state changed only on the edge of the controlling clock signal. • Two types of FF: • Edge Triggered FF • Level triggered FF DSD,USIT,GGSIPU

  6. VHDL code for gated D-FF • entity dff is • Port ( d : in std_logic; • clk : in std_logic; • reset: in std_logic; • q : out std_logic); • end dff; • architecture Behavioral of dff is • begin • process(clk,reset) • begin • if (reset ='1') then q <= '0'; • elsif (clk'event and clk='1') then • q <= d; end if; • end process; • end Behavioral; DSD,USIT,GGSIPU

  7. Waveform of D-ff DSD,USIT,GGSIPU

  8. Register • A flip-flop stores one bit of information. When a set of n flip-flops is used to store n bits of information, such as an n-bit number, it is called Register. • A common clock is used for each flip-flop in a register. DSD,USIT,GGSIPU

  9. A simple shift register DSD,USIT,GGSIPU

  10. Shift Left Register • entity shifleft is • Port ( newdata : in std_logic; • datain : in std_logic_vector(3 downto 0); • dataout : out std_logic_vector(3 downto 0); • clk : in std_logic; • reset : in std_logic); • end shifleft; • architecture Behavioral of shifleft is • begin • process (clk,reset,newdata) • begin • if (reset='1') then dataout <= "0000"; • elsif (clk'event and clk='0') then • dataout <= datain(2 downto 0) & newdata; • end if; • end process; • end Behavioral; DSD,USIT,GGSIPU

  11. Waveform of Shift Left DSD,USIT,GGSIPU

  12. VHDL code for Right Shift Register • entity shiftReg is • Port ( datain : in std_logic_vector(3 downto 0); • newdata : in std_logic; • dataout : out std_logic_vector(3 downto 0); • clk : in std_logic; • reset : in std_logic); end shiftReg; • architecture Behavioral of shiftReg is • begin • process(clk,reset) • begin • if (reset ='1') then dataout <= "0000"; • elsif (clk'event and clk='0') then • dataout <= newdata & datain(3 downto 1); • end if; • end process; • end Behavioral; DSD,USIT,GGSIPU

  13. Waveform of shift Right register DSD,USIT,GGSIPU

  14. VHDL code for shift register • entity shiftRegester is • Port ( reset,clk,w : in std_logic; q : out std_logic_vector(3 downto 0)); • end shiftRegester; • architecture Behavioral of shiftRegester is • signal temp : std_logic_vector(3 downto 0); • begin • process(clk,reset) • begin if (reset ='0') then q <= (others=>'0'); • elsif (clk'event and clk='1') then • genbits: for i in 3 downto 1 loop • temp(i) <= temp(i-1); • end loop; • temp(0) <= w; end if; • q <= temp; end process; • end Behavioral; DSD,USIT,GGSIPU

  15. Waveform of shift register DSD,USIT,GGSIPU

  16. Serial-in Serial-out Shift Register DSD,USIT,GGSIPU

  17. Serial in Parallel out DSD,USIT,GGSIPU

  18. counter • entity counterUP is • Port ( clk : in std_logic; • load: in std_logic; • d : in std_logic_vector(3 downto 0); • reset : in std_logic; • e : in std_logic; • q : out std_logic_vector(3 downto 0)); • end counterUP; DSD,USIT,GGSIPU

  19. architecture Behavioral of counterUP is • signal count: std_logic_vector(3 downto 0); • begin • process(clk,reset,load,d) • begin • if (load='1') then • count <= d; -- loadable counter • elsif (reset='0') then • count <= "0000"; • elsif (clk'event and clk='0') then • if (count="1001") then -- decade counter • count <= "0000" ; • elsif (e ='1') then • count <= count + 1; • else count <= count - 1; • end if; • end if; • end process; q <= count; end Behavioral; DSD,USIT,GGSIPU

  20. Waveform of counter design DSD,USIT,GGSIPU

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