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IO Controller Module

IO Controller Module. Arbitrates IO from the CCP Physically separable from CCP Can be used as independent data logger or used in future projects. Implemented using a Xilinx Spartan 3E FPGA (XCS500E-PQ208). FPGA Selection. FPGA chosen for highest gate & largest pin count

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IO Controller Module

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  1. IO Controller Module • Arbitrates IO from the CCP • Physically separable from CCP • Can be used as independent data logger or used in future projects. • Implemented using a Xilinx Spartan 3E FPGA (XCS500E-PQ208)

  2. FPGA Selection • FPGA chosen for highest gate & largest pin count • BGA is not desirable due to board routing complexity

  3. IOC Rigidware

  4. Main RAM • XC3S500E has 45KB of Block Memory • Approximately 40 KB will be used for Plasma CPU • RAM preloaded with boot loader

  5. SPI FLASH & MMC • Application code is stored on SPI Flash • Boot loader loads application into RAM • Same SPI bus is used for an SD card for logging • All typical SD cards support standard MMC protocol

  6. System Clock Counter • Provides timing information • Sourced from 50 MHz clock which allows for integer division to decade increments of time.

  7. Dedicated UART • Hardwired to USB-UART transceiver • Load new application code • Debug system during operation

  8. CCP Communication • Dual port ram allows for independent operation • High speed serial interface used to access shared RAM • Interrupt signals provided to and from CCP

  9. Analog Controller • Finite state machine responsible for acquiring analog data from ADC • Data available for direct access from CPU address space • Configures reference voltage DAC

  10. PWM Controller • FSM that arbitrates servo PWM generation and reading • Generator is configurable to provide servo format or full range duty cycles

  11. Configurable IO Ports • Each pin can be configured as input, output, or special function • Special functions include configurable SPI, I2C and UART modules • IP provided by OpenCores

  12. Configurable IO Ports • MAV peripheral set only requires 1 port • Preliminary logic estimates show that 5 ports should be possible

  13. IOC Hardware

  14. Programming Interface • USBUART converter does most of the work for us • PM FLASH is programmed from UART • Second UART is provided for CCP configuration

  15. FLASH & SD Card • SST’s 4MB FLASH stores application program • Shares SPI Bus with SD Card for data logging and removable storage

  16. CCP Interface • High speed serial interface to CCP along with interrupt requests • Pins on FPGA and header are reserved specifically for implementing GPMC in the future

  17. FPGA Configuration • On power-up, FPGA is automatically configured by the XCF02S which stores rigidware. • Rigidware can be changed via JTAG interface

  18. Analog to Digital Converter • Simultaneous samples of 8 channels • Supports differential inputs • Adjustable sampling range • Range is digitally controlled by adjacent DAC

  19. Digital IO • PWM signals connected directly to IOB (3.3v levels) • Configurable IO Ports have adjustable logic levels. • User supplies voltage reference • TXB0108 detects direction of communication without the need for direction control

  20. Logic Cost Analysis • Design with 5 IO ports uses approximately 80% of available logic • 20% for uncertainty in estimates and potential overhead for PAR of large designs.

  21. Throughput Estimation • Dummy DAQ program written for MAV set of peripherals • Single sample can be executed in ~420 clock cycles @ 25 MHz • Assuming SPI communication to IMU is done without interrupts, CPU must stall for duration of transfer (~200 cycles @ 2 MHz) • Results in theoretical sample rate of 30 kHz

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