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Class Design Project Test Generation

Class Design Project Test Generation. Hillary Grimes III ELEC7770 - Project Presentation April 26, 2007. Outline. Design For Testability (DFT) Full Scan Design Fault Models Stuck-At Faults Transition Delay Faults I DDQ Testing Results FastScan Multiple Fault Model Conclusion.

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Class Design Project Test Generation

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  1. Class Design Project Test Generation Hillary Grimes III ELEC7770 - Project Presentation April 26, 2007 Class Design Project - Test Generation

  2. Outline • Design For Testability (DFT) • Full Scan Design • Fault Models • Stuck-At Faults • Transition Delay Faults • IDDQ Testing • Results • FastScan • Multiple Fault Model • Conclusion Class Design Project - Test Generation

  3. Design For Testability • After 24 hours, FlexTest only achieved 13.5% stuck-at fault coverage for both designs • Solution: Full Scan Design • Possible to control & observe memory elements • Simplifies testing & ATPG complexity • All flip-flops replaced with scannable flip-flops: Class Design Project - Test Generation

  4. Full Scan Design • Scan elements connected to form scan chain • Basic scan test pattern: • Load scan chain • Apply primary inputs • Measure primary outputs • Apply clock • Unload scan chain • Disadvantages • Area Overhead • Performance Overhead Class Design Project - Test Generation

  5. Stuck-At Fault Model • Two faults per fault site (gate inputs & outputs) • Stuck-At 0 • Stuck-At 1 • Optimized For Area: • Uncollapsed: 69,732 • Collapsed: 49,871 • Optimized For Delay: • Uncollapsed: 70,112 • Collapsed: 49,921 Class Design Project - Test Generation

  6. Transition Delay Fault Model • Two faults per fault site (gate inputs & outputs) • Slow-To-Rise • Slow-To-Fall • Optimized For Area: • Uncollapsed: 69,732 • Collapsed: 59,242 • Optimized For Delay: • Uncollapsed: 70,112 • Collapsed: 59,292 Class Design Project - Test Generation

  7. IDDQ Testing – Pseudo Stuck-At Fault Model • IDDQ–Quiescent IDD Current • Measured Through VDD or VSS • Expensive–current measurement takes much longer than voltage measurement • 15 test vectors selected from final test set for IDDQ measurement Class Design Project - Test Generation

  8. Results - FastScan • 15 IDDQ vectors selected from Stuck-At Test Set • Area Optimized: 73.56% Test Coverage • Delay Optimized: 74.01% Test Coverage Class Design Project - Test Generation

  9. Multiple Fault Model • Generate one test set for both stuck-at & transition faults • Procedure • Generate transition delay test set • Simulate vectors to find stuck-at fault coverage • Add additional vectors to improve stuck-at fault coverage • After pattern compression, 15 vectors selected for IDDQ measurement Class Design Project - Test Generation

  10. Results - Multiple Fault Model • 15 IDDQ vectors selected • Area Optimized: 73.54% Test Coverage • Delay Optimized: 73.76% Test Coverage Class Design Project - Test Generation

  11. Conclusion • Multiple Fault Model ATPG • Reduced the number of compressed vectors for both designs • No change in stuck-at fault coverage • Reduced transition fault coverage • Area optimized: 96.79% to 94.07% • Delay optimized: 96.20% to 94.22% Class Design Project - Test Generation

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