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Lecture 5: Instruction Set Architecture (Review)

Lecture 5: Instruction Set Architecture (Review). Michael B. Greenwald Computer Architecture CIS 501 Spring 1999. Administration. Policies: no extensions on homework HW #2: shorter, fewer points, less time, HW manuals on line. Design Space of ISA. Five Primary Dimensions

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Lecture 5: Instruction Set Architecture (Review)

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  1. Lecture 5:Instruction Set Architecture(Review) Michael B. Greenwald Computer Architecture CIS 501 Spring 1999

  2. Administration • Policies: no extensions on homework • HW #2: shorter, fewer points, less time, HW manuals on line

  3. Design Space of ISA Five Primary Dimensions • Operand Storage Where besides memory? • Number of (explicit) operands ( 0, 1, 2, 3 ) • Effective Address How is memory location specified? • Type & Size of Operands byte, int, float, vector, . . . How is it specified? • Operations add, sub, mul, . . . How is it specifed? Other Aspects • Successor How is it specified? • Conditions How are they determined? • Encodings Fixed or variable? Wide? • Parallelism

  4. Continuum of ISA Classes • All can have arbitrary number of registers • Accumulator: each register is special, implicit in op-code • Stack: top-of-stack register cache • GPR: no special meaning, so can keep adding. • What values are stored in each register? • Accumulator: forced by instruction • Stack: mostly order of eval • GPR: almost no restrictions

  5. The Case Against Special Purpose Registers • Performance is derived from the existence of several fast registers, not from the way they are organized • Data does not always “surface” when needed • Constants, repeated operands, common subexpressions so TOP and Swap instructions are required • Code density is about equal to that of GPR instruction sets • Registers have short addresses • Keep things in registers and reuse them • Slightly simpler to write a poor compiler, but not an optimizing compiler

  6. Design Space of ISA Five Primary Dimensions • Operand Storage Where besides memory? • Number of (explicit) operands ( 0, 1, 2, 3 ) • Effective Address How is memory location specified? • Type & Size of Operands byte, int, float, vector, . . . How is it specified? • Operations add, sub, mul, . . . How is it specifed? Other Aspects • Successor How is it specified? • Conditions How are they determined? • Encodings Fixed or variable? Wide? • Parallelism

  7. General Purpose Registers • How many operands? (2 or 3) • How many operands access memory? (0 - 3)

  8. Dis/Advantages of 3 Common GPR Machines

  9. Architecture Names • Worth hearing once • Worth forgetting • Historically questionable • Non-standard definitions • e.g. Harvard Architecture, Von Neumann architecture, etc.

  10. Design Space of ISA Five Primary Dimensions • Operand Storage Where besides memory? • Number of (explicit) operands ( 0, 1, 2, 3 ) • Effective Address How is memory location specified? • Type & Size of Operands byte, int, float, vector, . . . How is it specified? • Operations add, sub, mul, . . . How is it specifed? Other Aspects • Successor How is it specified? • Conditions How are they determined? • Encodings Fixed or variable? Wide? • Parallelism

  11. Data in memory • Word size: 8,16,32,36,40,70,72... • Byte/character size: 7(KL10),8,9(Multics) • Addressing (pointer format) • Bit fields • Big-Endian vs. Little-Endian (wars) • Alignment • Unaligned accesses are slow: • require alignment network • sign extend • These are not evil in themselves, unless they slow down the aligned case by (e.g.) slowing down pipeline

  12. Computing the Effective Address • Addressing mode in instruction • Additional mode (tags) in data • Forwarding pointer (Lisp Machine) • Lookup/indirection (PDP-10)

  13. Kinds of Addressing Modes memory • Register direct Ri • Immediate (literal) v • Direct (absolute) M[v] • Register indirect M[Ri] • Base+Displacement M[Ri + v] • Base+Index M[Ri + Rj] • Scaled Index M[Ri + Rj*d + v] • Autoincrement M[Ri++] • Autodecrement M[Ri - -] • Memory Indirect M[ M[Ri] ] • [Indirection Chains] (PDP-10, LispM) reg. file Ri Rj v

  14. Design Space of ISA Five Primary Dimensions • Operand Storage Where besides memory? • Number of explicit operands ( 0, 1, 2, 3 ) • Effective Address How is memory location specified? • Type & Size of Operands byte, int, float, vector, . . . How is it specified? • Operations add, sub, mul, . . . How is it specifed? Other Aspects • Successor How is it specified? • Conditions How are they determined? • Encodings Fixed or variable? Wide? • Parallelism

  15. Specifying Data Types • Implicit in operation vs. tagged data • Tagged data: • Garbage collection • Generic arithmetic (generic functions) • Mostly obsolete (although hardware support for tagged data still exists, e.g. SPARC) • Encoded in opcode • Type generally known at compile time • Genericity usually done at function call, in software.

  16. Possible data types • Boolean • Bit String • Character, String, BCD (“Packed Decimal”) • Integer (2’s complement, n bit) • Floating Point (IEEE 754) But also ... • BitVector • Polynomial • Chess Move

  17. Design Space of ISA Five Primary Dimensions • Operand Storage Where besides memory? • Number of explicit operands ( 0, 1, 2, 3 ) • Effective Address How is memory location specified? • Type & Size of Operands byte, int, float, vector, . . . How is it specified? • Operations add, sub, mul, . . . How is it specifed? Other Aspects • Successor How is it specified? • Conditions How are they determined? • Encodings Fixed or variable? Wide? • Parallelism

  18. Classes of Operations • ALU + Floating Point • Load/Store • Control flow • Traps and protection • Synchronization • Cache/memory control • IO But don’t forget • EDITPC(VAX) • CRC(VAX) • BITBLT,EIEIO(PowerPC),CAS2 (68040),...

  19. Control Flow: Branches and Conditions

  20. Instruction Encoding: Issues • Size of compiled code • Speed of decoding • Number of resources (registers) and access methods (addressing modes)

  21. Instruction Encoding: Styles • Variable (VAX [1-53 bytes]) • Highest code density • Flexibility • Fixed (DLX, MIPS, SPARC, PowerPC, HP PA) • Easy to decode • Hybrid (Intel 80x86) • Multiple fixed sizes to provide better code density while still being easy to decode

  22. Case Study: Quantitative Analysis of Constants • 3 kinds of constants • Immediate literals • Displacement addressing mode • Branch Distances • Frequency • Range/magnitude

  23. Immediate Literals • For ALU, comparisons, MOV immediate to register for constant, & MOV immediate to register for address. • Frequency:

  24. Immediate Literals • For ALU, comparisons, MOV immediate to register for constant, & MOV immediate to register for address. • Frequency:

  25. Immediate Literals: Range • 0 implicit, 94% positive, on VAX, 32bits • 50-70% within 8 bits, 75-80% within 16 bits

  26. Frequency of addressing modes • Immediate and Displacement dominate

  27. Kinds of Addressing Modes memory • Register direct Ri • Immediate (literal) v • Direct (absolute) M[v] • Register indirect M[Ri] • Base+Displacement M[Ri + v] • Base+Index M[Ri + Rj] • Scaled Index M[Ri + Rj*d + v] • Autoincrement M[Ri++] • Autodecrement M[Ri - -] • Memory Indirect M[ M[Ri] ] • [Indirection Chains] (PDP-10, LispM) reg. file Ri Rj v

  28. Displacement Addressing Mode: Range • Widely distributed, tested on mach. w/16 bit displacement • 1% >= 16 bits, 12 bits = 75%, 16 bits = 99%

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