Computer Organization and Architecture William Stallings 8th Edition

1. Computer Organizationand Architecture William Stallings 8th Edition Chapter 5 Internal Memory

2. The two basic forms of semiconductor random access memory (RAM) are dynamic RAM (DRAM) and static RAM (SRAM). • SRAM is faster, more expensive, and less dense than DRAM, and is used for cache memory. DRAM is used for main memory. • To compensate for the relatively slow speed of DRAM, a number of advanced DRAM organizations have been introduced. The two most common are synchronous DRAM and RamBus DRAM. Both of these involve using the system clock to provide for the transfer of blocks of data.

3. Organization • The basic element of a semiconductor memory is the memory cell. • All semiconductor memory cells share certain properties: • They exhibit two stable (or semistable) states, which can be used to represent binary 1 and 0. • They are capable of being written into (at least once), to set the state. • They are capable of being read to sense the state.

4. Memory Cell Operation

5. The cell has three functional terminals capable of carrying an electrical signal. The select terminal is to select a memory cell for a read or write operation. • The control terminal indicates read or write. • For writing, the third terminal is to provide an electrical signal that sets the state of the cell to 1 or 0. For reading, that terminal is used for output of the cell’s state.

6. Semiconductor Memory Types

7. Random Access Memory (RAM) • The most common is referred to as random-access memory (RAM). • One distinguishing characteristic of RAM is that it is possible both to read data from the memory and to write new data into the memory easily and rapidly. • The other distinguishing characteristic of RAM is that it is volatile. • The two traditional forms of RAM used in computers are DRAM and SRAM.

8. Semiconductor Main Memory • Random Access Memory (RAM) • Misnamed as all semiconductor memory is random access. • Read/Write. • Volatile. • Temporary storage. • Static or dynamic.

9. Dynamic RAM (DRAM) • Bits stored as charge in capacitors. • Charges leak. • Need refreshing even when powered. • Simpler construction. • Smaller per bit. • Less expensive. • Need refresh circuits. • Slower. • Used for main memory. • Essentially an analogue device: • Level of charge determines value.

10. DRAM is made with cells that store data as charge on capacitors. The presence or absence of charge in a capacitor is interpreted as a binary 1 or 0. • The next diagram is a typical DRAM structure for an individual cell that stores 1 bit. The address line is activated when the bit value from this cell is to be read or written. The transistor acts as a switch that is closed (allowing current to flow) if a voltage is applied to the address line and open (no current flows) if no voltage is present on the address line.

11. Dynamic RAM (DRAM) Cell Structure

12. DRAM Operation • Address line active when bit is to be read or written. • Transistor switch closed (current flows). • For write operation: • Voltage signal is applied to the bit line. • High voltage for 1, low voltage for 0. • Then a signal is applied to the address line. • Transfers charge to the capacitor. • For read operation: • Address line is selected. • transistor turns on. • Charge on capacitor is fed out onto bit line to sense amplifier. • Sense amplifier compares capacitor voltage with reference value to determine if the cell has 0 or 1. • Capacitor charge must be restored

13. Static RAM (SRAM) • Bits stored as on/off switches. • No charges to leak. • No refreshing needed when powered. • More complex construction. • Larger per bit. • More expensive. • Does not need refresh circuits. • Faster. • Used for cache memory. • Digital device: • Uses flip-flops.

14. Static RAM (SRAM) Cell Structure

15. Static RAM (SRAM) Operation • Four transistors T1,T2,T3,T4 connected in an arrangement gives stable logic state. • State 1: • C1 high, C2 low • T1 T4 off, T2 T3 on • State 0: • C2 high, C1 low • T2 T3 off, T1 T4 on • Address line controls the two transistors T5 T6 by switch it on to allowing read or write operation.

16. Static RAM (SRAM) Operation • For write operation: • The desired bit value is applied to line B, while its complement is applied to line B’ . • This forces the four transistors (T1, T2, T3, T4) into the proper state. • For a read operation: • The bit value is read from line B.

17. Static RAM (SRAM) • A static RAM will hold its data as long as power is supplied to it. • Both states are stable as long as the direct current (dc) voltage is applied. • Unlike the DRAM, no refresh is needed to retain (hold) data.

18. SRAM versus DRAM • Both volatile. • Power needed to preserve data. • Dynamic Memory Cell: • Simpler to build, smaller. • More dense (smaller cells = more cells per unit area). • Less expensive. • Needs refresh circuitry. • Favoured for larger memory units. • Static Memory Cell: • Faster. • Used for cache memory (both on and off chip).

19. Read Only Memory (ROM) • It contains a permanent pattern of data that cannot be changed. • A ROM is nonvolatile. • While it is possible to read a ROM, it is not possible to write new data into it. • An important application of ROMs is: • Microprogramming. • Library subroutines. • Systems programs (BIOS). • Function tables.

20. Types of ROM • Written during manufacture: • Very expensive for small runs. • Programmable (once): • PROM. • Needs special equipment to program. • Read “mostly”: • Erasable Programmable (EPROM). • Erased by UV. • Electrically Erasable (EEPROM). • Takes much longer to write than read. • Flash memory. • Erase whole memory electrically.

21. Programmable ROM (PROM) • When only a small number of ROMs with a particular memory content is needed, a less expensive alternative is the programmable ROM (PROM). • It is nonvolatile and may be written into only once. For the PROM, • The writing process is performed electrically and may be performed by a supplier or customer at a time later than the original chip fabrication. • Special equipment is required for the writing or “programming” process. • PROMs provide flexibility and convenience.

22. Erasable Programmable (EPROM) • It is read and written electrically, as with PROM. • It can be altered multiple times and, like the ROM and PROM, holds its data virtually indefinitely. • For comparable amounts of storage, the EPROM is more expensive than PROM, but it has the advantage of the multiple update capability.

23. Electrically Erasable ProgrammableRead-Only Memory (EEPROM) • It is a read-mostly memory that can be written into at any time without erasing prior contents; only the byte or bytes addressed are updated. • It combines the advantage of non volatility with the flexibility of being updatable in place, using ordinary bus control, address, and data lines. • EEPROM is more expensive than EPROM and also is less dense, supporting fewer bits per chip.

24. Flash Memory • Like EEPROM, flash memory uses an electrical erasing technology. • An entire flash memory can be erased in one or a few seconds, which is much faster than EPROM. • In addition, it is possible to erase just blocks of memory rather than an entire chip. • Like EPROM, flash memory uses only one transistor per bit, and so achieves the high density.

25. Chip Logic • Semiconductor memory comes in packaged chips like in next slide. • Each chip contains an array of memory cells. • For semiconductor memories, one of the key design issues is the number of bits of data that may be read/written at a time. At one extreme is an organization in which the physical arrangement of cells in the array is the same as the logical arrangement (as perceived by the processor) of words in memory. • The array is organized into W words of B bits each. For example, a 16-Mbit chip could be organized as 1M 16-bit words.

27. Organisation in detail • A 16Mbit chip can be organised as 1M of 16 bit words. • A bit per chip system has 16 lots of 1Mbit chip with bit 1 of each word in chip 1 and so on. • A 16Mbit chip can be organised as a 2048 x 2048 x 4bit array (211 x 211 x 22) = 224 = 16Mbit = 22 x 220 bit. • Reduces number of address pins. • Multiplex row address and column address. • 11 pins to address (211 = 2048). • Adding one more pin doubles range of values so x4 capacity.

28. Refreshing • Refresh circuit included on chip. • Disable DRAM chip while all data cells are refreshed. • Count through rows. • The data are read out and written back into the same location. This causes each cell in the row to be refreshed. • Takes time. • Slows down apparent performance.

29. Typical 16 Mb DRAM (4M x 4)

30. Chip Packaging • An integrated circuit is mounted on a package that contains pins for connection to the outside world. • Next diagram shows an example EPROM package, which is an 8-Mbit chip organized as 1M x 8 = 220 x 8. • The pins support the following signal lines: • The address of the word being accessed (A0–A19). • The data to be read out, consisting of 8 lines (D0–D7). • The power supply to the chip (Vcc). • A ground pin (Vss). • A chip enable (CE) pin. • A program voltage (Vpp) that is supplied during programming (write operations).

31. Packaging Typical Memory Package Pins and Signals

32. 256kByte = 28 x 210 x 8 Module Organisation

33. 1MByte Module Organisation

34. Interleaved Memory • Main memory is composed of a collection of DRAM memory chips. • A number of chips can be grouped together to form a memory bank. • Banks independently service read or write requests. • K banks can service k requests simultaneously, increasing memory read or write rates by a factor of K.

35. Error Correction • A semiconductor memory system is subject to errors. • These can be categorized as hard failures and soft errors. • A hard failure is a permanent physical defect so that the memory cell or cells affected cannot reliably store data but become stuck at 0 or 1 or switch erratically between 0 and 1. • Hard errors can be caused by harsh environmental abuse, manufacturing defects, and wear.

36. Error Correction • A soft error is a random, nondestructive event that alters the contents of one or more memory cells without damaging the memory. • Soft errors can be caused by power supply problems or alpha particles. • Both hard and soft errors are clearly undesirable, and most modern main memory systems include logic for both detecting and correcting errors.

37. Error Correction • Hard Failure. • Permanent defect. • Soft Error • Random, non-destructive. • No permanent damage to memory. • Detected using Hamming error correcting code.

38. Error Correcting Code Function ((Read ((Write new code M + K bits old code

39. Codes that operate in this fashion are referred to as error-correcting codes. • A code is characterized by the number of bit errors in a word that it can correct and detect. • The simplest of the error-correcting codes is the Hamming code devised by Richard Hamming at Bell Laboratories. • It depends on developing a code which can detect and correct single-bit errors in 8-bit words.

41. Hamming Error-Correcting Code • By applying the Hamming code, the comparison logic receives as input two K-bit values. A bit-by-bit comparison is done by taking the exclusive-OR (XOR) of the two inputs. • The result is called the syndrome word. Thus, each bit of the syndrome is 0 or 1 according to if there is or is not a match in that bit position for the two inputs. • The syndrome word is K bits wide and has a range between 0 and 2K -1. The value 0 indicates that no error was detected, if there is an error, which bit was in error.

43. Hamming Error-Correcting Code • An error could occur on any of the M data bits or K check bits, we must have: 2K - 1 >=M + K • When 4-bit syndrome word is generated for an 8-bit data word with the following characteristics: • If the syndrome contains all 0s, no error has been detected. • If the syndrome contains one and only one bit set to 1, then an error has occurred in one of the 4 check bits. No correction is needed. • If the syndrome contains more than one bit set to 1, then the numerical value of the syndrome indicates the position of the data bit in error. Then this data bit is inverted for correction.

45. Each check bit operates on every data bit whose position number contains a 1 in the same bit position as the position number of that check bit. • For example, by assuming that the 8-bit input word is 00111001, with data bit D1 in the rightmost position. The calculations are as follows: C1 = 1 ⊕ 0⊕ 1⊕ 1 ⊕ 0 = 1 C2 = 1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 = 1 C4 = 0 ⊕ 0 ⊕ 1 ⊕ 0 = 1 C8 = 1 ⊕ 1 ⊕ 0 ⊕ 0 = 0

46. Suppose now that data bit 3 sustains an error and is changed from 0 to 1. • When the check bits are recalculated, we have: C1 = 1 ⊕ 0⊕ 1⊕ 1 ⊕ 0 = 1 C2 = 1 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 0 = 1 C4 = 0 ⊕ 1 ⊕ 1 ⊕ 0 = 1 C8 = 1 ⊕ 1 ⊕ 0 ⊕ 0 = 0

47. ⊕ • When the new check bits are compared with the old check bits, the syndrome word is formed: C8 C4 C2 C1 0 1 1 1 0 0 0 1 ----------------------- 0 1 1 0 • The result syndrome word is 0110, indicating that bit position 6, which contains data bit 3, is in error. • The code just described is known as a single-error-correcting (SEC) code. More commonly, semiconductor memory is equipped with a single-error-correcting, double-error-detecting (SEC-DED) code.

49. Advanced DRAM Organization • Basic DRAM same since first RAM chips. • Enhanced DRAM. • Contains small SRAM as well. • SRAM holds last line read. • Cache DRAM • Larger SRAM component. • Use as cache or serial buffer.

50. Synchronous DRAM (SDRAM) • Access is synchronized with an external clock. • Address is presented to RAM. • RAM finds data (CPU waits in conventional DRAM). • Since SDRAM moves data in time with system clock, CPU knows when data will be ready. • CPU does not have to wait, it can do something else. • Burst mode allows SDRAM to set up stream of data and fire it out in block. • DDR-SDRAM sends data twice per clock cycle (leading & trailing edge).