1 / 16

Estimation of Single Event Upset Probability Impact of FPGA Designs

Estimation of Single Event Upset Probability Impact of FPGA Designs. Prasanna Sundararajan, Scott McMillan, Brandon Blodget, Carl Carmichael, Xilinx Inc Cameron Patterson Virginia Tech. Introduction.

karah
Télécharger la présentation

Estimation of Single Event Upset Probability Impact of FPGA Designs

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Estimation of Single Event Upset Probability Impact of FPGA Designs Prasanna Sundararajan, Scott McMillan, Brandon Blodget, Carl Carmichael, Xilinx Inc Cameron Patterson Virginia Tech

  2. Introduction • Single Event Upsets (SEUs) on a SRAM based FPGA may impact the functionality of the programmed circuit • FPGA designs do not utilize all memory cells • SEUPI tool estimates the probability that an SEU will alter a memory cell utilized by a specific design • SEUPI augments Mean Time Between Failure (MTBF) calculations with design specific information

  3. Motivation • Increase in use of SRAM FPGAs in space applications • Provide accurate MTBF information in order to make intelligent mitigation decisions • Rise in configuration cells mandates a SEU susceptibility estimation for FPGA systems placed in high-altitude to determine a need for mitigation strategy

  4. VDD VDD OFF ON Sensitive Area Sensitive Area I Q Difff ON OFF GND t(nS) Single Event Upset • A single high-energy particle can strike a critical node and leave behind an ionized track • If value of this charge is high enough, a voltage of sufficient value can cause a bit flip called soft error.

  5. Single Event Upsets • Caused by • Atmospheric neutrons • Alpha particles • Soft error can be mitigated by reconfiguring the FPGA configuration memory • SEUs in configuration memory of FPGA is the focus of this paper

  6. SEU Impact Dependency Factors • SEU Impact Depends on • Altitude: ~10x worse @10,000Ft vs. sea level • Latitude: ~6x worse at North Pole vs. Equator • Neutron Flux: 120neutrons/cm2-hr impact everything (@ 45° latitude) • Area cross section per configuration bit • % Resource utilization of a FPGA Device

  7. 0.18 m 0.35 m 0.22 m 0.15 m FPGA Architectures And Configuration Bits • Rise in configuration bits due to advancement in process technology

  8. Alternate Methods • Controlled exposure of FPGAs to high energy particle beam • Performed by exposing FPGAs to high energy particle generator • SEU study at Xilinx • Large number of FPGAs exposed to atmosphere and upsets are recorded

  9. Alternate Methods • Hardware SEU simulator by Los Alamos Laboratory and Brigham Young University • SEU simulated by dynamically corrupting one bit at a time • Mean Time Between Upset • SEU susceptibility estimated by assuming all the device configuration bits are susceptible to SEUs

  10. Single Event Upset Probability Impact (SEUPI) • Tool developed for static estimation of bits susceptible to SEUs • Estimates provided specific to a FPGA design • Estimation technique based on accounting the resources used in a user design • SEUPI is a ratio of bits used in a specific design to total number of device configuration bits

  11. Device Config Bits % Care Bits Single Event Upset Probability Impact (SEUPI) • Estimate % of configuration bits used in a design a.k.a Care Bits • Care bits depends on resource (pips, muxes, LUTs, FFs) utilization in a design

  12. FPGA Design NCD Tools to identify resource used Resource Usage List SEUPI Map Resource & Bits JBits Data Model SEUPI Tool Flow Report Care Bits Device Resource & Config Bits Model

  13. Results • Design 1 • 8109/10752 slices (75%) • 369/624 IOBs (59%) • 27628 Signals • Design 2 • 19401/22400 slices (86%) • 408/912 IOBs (45%) • 56121 Signals

  14. SEUPI Pros & Cons • Pros • No investment needed to procure hardware simulator • Controlled experiment using high energy particle accelerators can be avoided • Inexpensive estimate specific to an user design • Suitable if worst case static estimate is desired • Cons • As this is a worst case estimate, the susceptibility estimate is high compared to other estimation techniques

  15. MTBF Calculation • Mean Time Between Failure • MTBU = 1  (Area cross section per bit * neutron flux * device config bits) • SEUPI = Care Bits / Total Device Configuration Bits • MTBF = MTBU / SEUPI

  16. Summary & Future Work • Estimation of susceptibility to SEU important to build reliable FPGA systems • SEUPI tool can be used for static estimation • SEUPI tool can be used to estimate without the need for SEU hardware or high energy accelerators • Results obtained from SEUPI tool would be validated with hardware simulator tool

More Related