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IKI10230 Pengantar Organisasi Komputer Kuliah no. 11: Control Unit

IKI10230 Pengantar Organisasi Komputer Kuliah no. 11: Control Unit. Sumber : 1. Paul Carter, PC Assembly Language 2. Hamacher. Computer Organization , ed-5 3. Materi kuliah CS61C/2000 & CS152/1997, UCB. 5 Mei 2004 L. Yohanes Stefanus (yohanes@cs.ui.ac.id) Bobby Nazief (nazief@cs.ui.ac.id)

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IKI10230 Pengantar Organisasi Komputer Kuliah no. 11: Control Unit

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  1. IKI10230Pengantar Organisasi KomputerKuliah no. 11: Control Unit Sumber:1. Paul Carter, PC Assembly Language2. Hamacher. Computer Organization, ed-53. Materi kuliah CS61C/2000 & CS152/1997, UCB 5 Mei 2004 L. Yohanes Stefanus (yohanes@cs.ui.ac.id)Bobby Nazief (nazief@cs.ui.ac.id) bahan kuliah: http://www.cs.ui.ac.id/kuliah/POK/

  2. Computer Processor (active) Memory (passive) (where programs, data live when running) Devices Input Control (“brain”) Datapath (“brawn”) Output Prosesor: Control & Datapath

  3. Control lines Instruction Decoder PC Address lines MAR IR Memory bus Data lines MDR R0 Y R(n-1) Add ALU control lines Sub ALU XOR Carry-in TEMP Z Review: Organisasi Prosesor (Single-bus) Control Unit DatapathUnit

  4. ALU PC Clk Interaksi Memori  [Control,Datapath] Control Ideal Instruction Memory Control Signals Conditions Instruction Rd Rs Rt 5 5 5 Instruction Address A Data Address Data Out 32 Rw Ra Rb 32 Ideal Data Memory 32 Registers Next Address Data In B Clk Clk 32 Datapath

  5. Instruction IR Control Conditions ADD MARin Control Signals PCout Riin Datapath Interaksi Control  Datapath STEPCONTROL SIGNALS 1. PCout, MARin, Read, Clear Y, Set carry-in to ALU, Add, Zin 2. Zout, PCin, WMFC 3. MDRout, IRin 4. R3out, MARin, Read 5. R1out, Yin, WMFC 6. MDRout, Add, Zin 7. Zout, R1in, End

  6. Pengendalian Eksekusi Instruksi: Hardwired Control

  7.   Hardwired Control Organization CLK Clock Reset Control StepCounter  Step Decoder T1 T2Tn IR Encoder Instruction Decoder MOV Status Flags ADD   Condition Codes INSn  Run End Control Signals

  8. JMP ADD T6 T5 T1   Zin Hardwired Control Encoding • Fungsi Logika: Zin = T1 + T6 ADD + T5 JMP + … • Zin akan terjadi pada: • T1: untuk setiap instruksi (instruksi berikut: PC+1) • T5: untuk instruksi ADD • T6: untuk instruksi JMP

  9. Pengendalian Eksekusi Instruksi: Microprogrammed Control

  10. Microprogramming • Control is the hard part of processor design ° Datapath is fairly regular and well-organized ° Memory is highly regular ° Control is irregular and global • Microprogramming: • -- A Particular Strategy for Implementing the Control Unit of a • processor by "programming" at the level of register transfer • operations • Microarchitecture: • -- Logical structure and functional capabilities of the hardware as • seen by the microprogrammer • Historical Note: • -- IBM 360 Series first to distinguish between architecture & organization • -- Same instruction set across wide range of implementations, each with • different cost/performance

  11. Microinstructions IRin PCin PCout MARin MDRout Yin R1in R1out R3out Zin Zout Clear Y Carry-in Add Read WMFC End STEPCONTROL SIGNALS 1. PCout, MARin, Read, Clear Y, Carry-in to ALU, Add, Zin 2. Zout, PCin, WMFC 3. MDRout, IRin 4. R3out, MARin, Read 5. R1out, Yin, WMFC 6. MDRout, Add, Zin 7. Zout, R1in, End 1 2 3 4 5 6 7

  12. IR Status Flags Condition Codes Decoding Circuits μAR Control Store μIR Next Address μInstruction Decoder  Control Signals Microinstruction Organization

  13. F3 F2 F1 F0 (8 bits) (3 bits) (3 bits) (3 bits) F10 F9 F8 . . . (1 bit) (1 bit) (1 bit) Microinstruction Encoding 000: No transfer 001: PCout 010: MDRout 011: Zout 100: Rsrcout 101: Rdstout 000: No transfer 001: MARin 010: MDRin 011: TEMPin 100: Yin 000: No transfer 001: PCin 010: IRin 011: Zin 100: Rsrcin 101: Rdstin Address of next microinstruction F4 (4 bits) 0: NextAdrs 1: InstDec 0: No action 1: ORmode 0: No action 1: ORindsrc 0000: ADD 0001: SUB . . 1111: XOR

  14. Content of μStore 000 001 002 003 121 122 170 171 172 173

  15. /Etc

  16. “Macroinstruction” Interpretation User program plus Data this can change! Main Memory ADD SUB AND . . . one of these is mapped into one of these DATA execution unit AND microsequence e.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s) CPU control memory

  17. Control: Hardware vs. Microprogrammed • Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique. Initial Representation Finite State Diagram Microprogram Sequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMs Logic Representation Logic Equations Truth Tables Implementation Technique PLA ROM “hardwired control” “microprogrammed control”

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