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Low Power IP Design Methodology for Rapid Development of DSP Intensive SOC Platforms

Low Power IP Design Methodology for Rapid Development of DSP Intensive SOC Platforms. T. Arslan A.T. Erdogan S. Masupe C. Chun-Fu D. Thompson. Contents. Introduction to power consumption Introduction to Main Concepts Low Power Design Methodology IP implementations Results and conclusions.

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Low Power IP Design Methodology for Rapid Development of DSP Intensive SOC Platforms

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  1. Low Power IP Design Methodology for Rapid Development of DSP Intensive SOC Platforms T. ArslanA.T. ErdoganS. MasupeC. Chun-FuD. Thompson

  2. Contents • Introduction to power consumption • Introduction to Main Concepts • Low Power Design Methodology • IP implementations • Results and conclusions

  3. Power Consumption in CMOS-Based DSP Systems

  4. Common Approaches to Low Power Design • Supply Voltage Reduction • Clock Gating Disadvantage: • Added design effort

  5. Systematic Low Power Design Approach Exploit Algorithmic Correlations and Redundancies within an algorithm, then Map to hardware.

  6. Systematic Design Implementation Framework Performance Criteria Ordering algorithm Data representation Multiplier SC, Bus SC Library CAD DSP Algorithm Block, Segmentation, etc. Verilog/VHDL Component Library Synthesis Netlist

  7. P Rapid Design and IP-Based Integration Platforms IPx WL IP N . . . . . . # Multiplier Algorithm IPy

  8. Developed IPs

  9. Parameterisation Options

  10. Design Flow for Filter IPs

  11. FIR Filter Implementation

  12. Typical Single Multiplier DSP Processor Architecture

  13. Transpose Direct Form (TDF) FIR Structure

  14. Modified DSP Processor Architecture for TDF FIR Filter Implementation

  15. An Example SFG for IP2

  16. Coefficient Memory Configuration with Coefficient Ordering Order coefficients such that adjacent coefficients are highly correlated.

  17. Coefficient Word: SF : Shift Flag SF = 1 shift SF = 0 no shift PCVMA : Pre-Calculated Value Memory Address

  18. Coefficient Word Decomposition (Verilog Code)

  19. An Example SFG for IP3

  20. Memory Operations (Verilog Code)

  21. Software Implementation Example for IP3

  22. Power Evaluation

  23. Filter Specifications

  24. Power Reductions Achieved (wordlength = 16 bit)

  25. An example of a 6-tap FIR filter with block size of 3

  26. Power Reductions for IP4 (wordlength = 16 bit)

  27. Reductions in Number of Memory Accesses (%)

  28. Coefficient Segmentation Algorithm

  29. Example Segmentations

  30. Example Segmentations

  31. Coefficient Segmentation Algorithm for Two’s Complement Coding

  32. Coefficient Segmentation Algorithm for Sign-Magnitude Coding

  33. Total switching activity of H and M coefficient sets with Two’s Complement Coding

  34. Total switching activity of H and M coefficient sets with Sign-Magnitude Coding

  35. Simplified Filter Architecture for Mixed-Mode Multiplication

  36. ( sign magnitude) ( sign magnitude) Multiplier Data Coefficient ( sign) Memory Memory Sign two’s à Control Add Acc Output Simplified Filter Architecture for Sign-Magnitude Multiplication

  37. Example Switching Activity Distribution with Two’s Complement Coding (N=89, W=16)

  38. Example Switching Activity Distribution with Sign-Magnitude Coding (N=89, W=16)

  39. Power Reductions Achieved with Coefficient Segmentation

  40. Power Reduction in Multiplier Circuit (wordlength = 16 bit) 35% 47% 44% 53% 62%

  41. Power Reduction (wordlength = 16 bit)

  42. Power Reduction at Coefficient Bus (wordlength = 16 bit) 37% 37% 49% 54% 54%

  43. DCTImplementationScheme

  44. 2-D DCTImplementationApproach

  45. Simplified Architecture of the DCT Processor

  46. Conventional Programmable FIR Filter Architecture

  47. TDF with Coefficient Ordering Programmable FIR Filter Architecture

  48. Power Reduction (%)

  49. Coefficient Data t NC Output IP1 Reset Of/ Uf Load Clock Top View of IP1

  50. Block Report for IP1

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