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CPRE 211 Summary

2. Exam 3. MPC555 on-chip I/O and interrupt systemsGeneral concepts of interruptInterrupt overheadInterrupt vs. exceptionMPC555 interrupt sourcesMPC555 interrupt controller and its registersMPC555 ESR programmingPIT programming. 3. Exam 3. MPC555 QADC64ADC basics and formulasSuccessive App

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CPRE 211 Summary

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    1. 1 CPRE 211 Summary

    2. 2 Exam 3 MPC555 on-chip I/O and interrupt systems General concepts of interrupt Interrupt overhead Interrupt vs. exception MPC555 interrupt sources MPC555 interrupt controller and its registers MPC555 ESR programming PIT programming

    3. 3 Exam 3 MPC555 QADC64 ADC basics and formulas Successive Approximation QADC64 programming CCW table layout CCW format QADC configurations

    4. 4 Exam 3 MPC555 TPU3 TPU basics Waveform and events TPU configurations General TPU function interface General programming procedure Input capture function Output compare function

    5. 5 MPC555 Exceptions and Interrupts

    6. 6 Vectored Interrupts:PPC

    7. 7 MPC555 Exception Processing Key point: ALL register values, if changed, must be saved and restored Include r0-r31, CR, LR, XER, PC, MSR and others ESR should save those register contents Can use stack But the CPU has changed the contents of PC and MSR!

    8. 8 MPC555 Exception Processing SRR0/SRR1: To save PC and MSR Solution: Use special registers to help save them SRRx: Machine status Save/Restore Registers SRR0 saves PC, SRR1 saves the changed bits in MSR How it works: The CPU saves PC to SRR0, MSR to SRR1* The ESR saves SRR0/SRR1 into stack

    9. 9 MPC555 Interrupt Controller Programming interface SIPEND: Interrupt pending register, recording all pending interrupt signals SIMASK: Interrupt mask register, storing the mask bits SIVEC: Interrupt vector code, storing the vector code for the interrupt of the highest priority

    10. 10 MPC555 Interrupt Controller SIPEND: Eight internal interrupt sources, eight external interrupt sources; interleaved together UIPEND is located at UIMB

    11. 11 MPC555 Interrupt Controller SIMASK: 16 effective bits, one for each interrupt source

    12. 12 MPC555 Interrupt Controller SIVEC: Vector code for the most urgent interrupt

    13. 13 External Interrupt Exception Prologue (Continue) ; STEP 4: DETERMINE INTERRUPT SOURCE lis r3, SIVEC@ha lbz r3, SIVEC@l (r3) lis r4, IRQ_table@h ori r4, r4, IRQ_table@l add r4, r3, r4 mtlr r4 ; STEP 5: BRANCH TO INTERRUPT HANDLER blrl

    14. 14 Periodic Interrupt Timer Timer has many uses To implement a clock To check user input periodically To monitor environment changes To switch between programs

    15. 15 Analog-to-digital converters

    16. 16 ADC: Digital Encoding Guessing the encoding is similar to finding an item in a list. Sequential search counting up: start with an encoding of 0, then 1, then 2, etc. until find a match. 2n comparisons: Slow! Binary search successive approximation: start with an encoding for half of maximum; then compare analog result with original analog input; if result is greater (less) than the original, set the new encoding to halfway between this one and the minimum (maximum); continue dividing encoding range in half until the compared voltages are equal n comparisons: Faster, but more complex converter ? Takes time to guess the encoding: start conversion input, conversion complete output

    17. 17 ADC using successive approximation Given an analog input signal whose voltage should range from 0 to 15 volts, and an 8-bit digital encoding, calculate the correct encoding for 5 volts. Then trace the successive-approximation approach to find the correct encoding. Assume M = 2n 1 a / Vmax = d / M 5 / 15 = d / (256 - 1) d = 85 or binary 01010101

    18. 18 Terms & Equations Bit Weight: analog value corresponding to a bit in the digital number Let AV be Analog Value; DN be Digital Number: AV = DN * Step Size + Offset = DN / 2n * Span + Offset DN = (AV - Offset) / Step Size = (AV - Offset) * 2n / Span

    19. 19 MPC555 QADC64

    20. 20 QADC Interface Total conversion time: initial sample time, final sample time, and resolution time Initial sample time time during which the selected input channel is driven by the buffer amplifier onto the sample capacitor (disabled by means of the BYP bit in the CCW) Final sampling period time to set up DAC array Resolution period time to convert voltage in the DAC array to a digital value

    21. 21 Programming QADC64 CCW Format:

    22. 22 TPU

    23. 23 TPU Block Diagram

    24. 24 TPU Timers

    25. 25 Events and Waveform

    26. 26 Channel Initialization

    27. 27 Channel Priority

    28. 28 Channel Function Activation

    29. 29 Host Sequence

    30. 30 Shared Register Modification

    31. 31 General Parameter Memory Map

    32. 32 Channel Programming

    33. 33 Input Capture Parameters

    34. 34 Channel Control Options

    35. 35 Frequency Measurement (FQM) Measures frequency of events. (pulse_count/window_size)

    36. 36 FQM Parameters Function code: 0xC Channel control: TBS: 0000 (capture, match TCR1) ; PAC: 001 rising edge or 010 falling edge; PSC: 11 input. Host Sequence (HSQR): 00 begin with falling edge, single shot; 01 begin with falling edge continual mode; 10 begin with rising edge, single shot; 11 begin with rising edge continual mode. Host service (HSRR): 10 initialize, 00 reset

    37. 37 TPU Programming in C

    38. 38 Output Compare (OC)

    39. 39 OC Parameters

    40. 40 OC Programming

    41. 41 OC Channel Control Options

    42. 42 OC Channel Control

    43. 43 CPRE 211 Summary Embedded systems concepts: applications, requirements, examples, etc. Computer organization concepts: CPU, memory, I/O devices, interconnects Machine-level programming basics Machine execution model Register, memory, I/O ports Arithmetic/logic, load/store, and control instructions Instruction encoding

    44. 44 CPRE 211 Summary C/Assembly programming Program layout: text, data, stack, heap, I/O space Control statements Function, stack/register usage, and EABI Interrupt system and programming Interrupt request lines and Interrupt controller Exception handler and interrupt handler System and device initialization

    45. 45 CPRE 211 Summary Programming MPC555 I/O Devices PIT Periodic Interrupt Timer QADC64 Queued ADC ADC/DAC principles and algorithm QADC64 execution model Host interface: CCW Table and Result Table etc. TPU Time Processor Unit Application background Hardware/software organization Host Interface function select, priority setting, parameter memory, etc.

    46. 46 CPRE 211 and Other Courses CPRE 305: Computer organization CPRE 308: Operating System CPRE 483: Hardware/software integration CPRE 488X: Embedded system design

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