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The passage of time

The passage of time. Being aware of time is critically important to many embedded systems Delays in software systems so they won’t overrun users Real-time clocks De-bouncing switches Knowing when to sample inputs Producing precisely-timed outputs Many internal uses Many other uses.

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The passage of time

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  1. The passage of time • Being aware of time is critically important to many embedded systems • Delays in software systems so they won’t overrun users • Real-time clocks • De-bouncing switches • Knowing when to sample inputs • Producing precisely-timed outputs • Many internal uses • Many other uses

  2. Time basis – Clock cycles • We will use a well-timed periodic signal as our time basis – a clock signal • Usually a square wave with a 50% duty cycle • Stability is desired – the more stable it is, the more accurate timing measurements may be • Period (s) = time from rising edge to the next rising edge • Frequency (Hz) = 1/Period • PSoC supports a wide variety of clock signals – stay tuned…

  3. Timing instruments • Counters – Count once per clock cycle • Can check count at any time (polling) – just like reading a clock • May set a flag or interrupt to “go off” at a certain time - like setting an alarm on a clock • Timers – Count once per clock cycle until an event occurs • Similar to using a stopwatch • Stops counting (and records the time) when an event occurs • “Event” usually means a rising edge on an input pin • May generate an interrupt on capture

  4. Counter Example – Interrupt once every 100ms • Select a clock with a 1ms period (1000Hz) • (more on this later) • Choose an counter that can count to at least 100 • An eight-bit counter will work for up to 256 counts • Determine how many counts equal 100ms • 100ms / 1ms =100 counts • But, PSoC counters are 0-based, so use 99 • Set up counter to count from 0 to 99 and reset • After 100 cycles, will reset and start over • Enable an interrupt for when count reaches 99 • Will generate an interrupt each 100ms

  5. Timer Example – Time (in ms) a response • Example – Time (in ms) how long for an ultrasonic echo to arrive. • Spec: Need 0.1ms resolution, up to 0.1s (1000 counts) • Choose a 16-bit timer (need to count to at least 1000) • Configure its clock to 0.1ms • Set up its capture input to hardware that produces a rising edge when response is received • An ultrasonic microphone connected to a little HW • Turn on interrupt on capture • Start the timer when the source signal is sent • Send out an ultrasonic pulse and start time • When interrupt received, read the timer • Count is the number of tenths of ms the response is delayed

  6. PSoC Clock Sources • All PSoC clock sources are derived from the 24MHz Internal Main Oscillator (IMO) • Generated internally, +/- 2.5% • Or externally, using a 32768Hz external crystal • Available as SYSCLK = Oscillator * 732 = 23.986MHz • Also, SYSCLK*2 (48MHz) is available • The CPU clock is produced by dividing SYSCLK by either: • 1 – 24MHz; 2 – 12 MHz; 4 – 6 MHz; 8 – 3MHz • 16 – 1.5MHz; 32 – 750KHz; 128 – 185.5KHz • 256 – 93.75KHz • Configured in Global Resources of Device Editor

  7. More PSoC Clocks • Individual digital and analog blocks may be clocked by one of three main clocks • VC1 – SYSCLK divided by 1-16 (24MHz – 1.5MHz) • VC2 – VC1 divided by 1-16 (24MHz – 93.75KHz) • VC3 – Either VC2, VC1, SYSCLK or SYSCLK*2 divided by 1-256 • (48MHz – 366.2Hz) • Some blocks may be clocked by the Internal Low Speed Oscillator (ILO or CPU_32KHz) as well • Always 32768 Hz

  8. Optional Ext clock The Big Clock Picture 48MHz SYSCLK*2 IMO/SYSCLK – 24MHz Divider for CPU clock Ext Crystal Source Dividers for VC1,2,3 ILO – 32KHz Sleep timer

  9. PSoC Counters Period register – Reloaded into counter when zero reached Optionally check against compare register value and set output high if count less than compare (can be used to adjust duty cycle of output) Down counter8-32 bits wide Enable tocount Lots and lotsof clock sourceoptions Optionally createinterrupt on eithercompare or terminalcount Terminal Count(zero) Indicator

  10. Configure a counter to interrupt every 10ms Divide 10KHz clock by 100 Period: 99(0 based) 8-bitCounter Compare: 0(unused) Enable: 1 Compare/TC out:unused Clock source: VC3 = IMO/16/15/10 = 24MHz/16/15/10 = 10000Hz Interrupt onTerminalCount

  11. Configure a counter to create a 1MHz square wave with 40% duty cycle On period = 400ns, off period = 600nsWith 24MHz clock, off = 14 cycles, on = 10 cycles Period: 23(0 based) 8-bitCounter Compare: 10 Compare type:Less-than (on for 0-9) Output to pin Enable: 1 TC out:unused Clock source: VC1 = SYSCLK / 1 = 24MHz Interrupt unused

  12. PSoC Counter API (8 bit example) • Counter8_start • Use to start it up • Counter8_EnableInt • If you want an interrupt • Counter8_WritePeriod • Put period in A, change at any time • Counter8_WriteCompareValue • Put compare value in A, change at any time

  13. PSoC Timers Optionally checkagainst compareregister value.Compare registeralso stores eventcapture time. Period register – Reloaded into counter when zero reached (set to max for timers) Optionally createinterrupt on compare, terminal count, or capture Down counter8-32 bits wide Capture Input – Stores count value in compareregister Lots and lotsof clock sourceoptions Terminal Count(zero) Indicator Timers are counters that have the ability to store (capture) the time of an external event (rising edge).

  14. Measure response time using a timer Assert an output and measure the time until a response is received. Time range is 0-2 seconds, with a resolution of 1ms = 2001 values. Compare reg holdstime of capture Down counter16 bits wide Period: 0xFFFF Interrupt on capture Capture tied toport pin. 1000Hz clock:VC3 = 24MHz/16/10/150 Software: Main starts timer, asserts output and enables capture interrupt.Interrupt subtracts 0xFFFF – Capture time = elapsed time in ms.

  15. Find the period/frequency of an input signal Measure the period of an input square wave signal. Frequency range is 100 – 100,000 Hz (10,000 µs – 10 µs period). Resolution is 1 µs. Compare reg holdstime of capture Down counter16 bits wide Period: 0xFFFF Interrupt on capture Capture tied toport pin. 1MHz clock:VC2 = 24MHz/8/3 Software: Main starts timer, enables capture interrupt.Interrupt keeps track of last two captures and subtracts previous – current time  period in µs.

  16. PSoC Timer API (16 bit example) • Timer16_1_Start • Use to start it up • Timer16_1_EnableInt • If you want an interrupt – source selected in device editor • Timer16_1_WritePeriod • Put period in X,A change at any time • Timer16_1_wReadCompareValue • Read compare value into X,A

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