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FYP PROJECT PRESENTATON

FYP PROJECT PRESENTATON. Alan Concannon 4ECE Supervisor: Dr Fearghal Morghan Co-Supervisor:John Maher. Presentation Overview. Project Description/Specification Current Progress Future Work. Project Specification(Original).

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FYP PROJECT PRESENTATON

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  1. FYP PROJECT PRESENTATON Alan Concannon 4ECE Supervisor: Dr Fearghal Morghan Co-Supervisor:John Maher

  2. Presentation Overview Project Description/Specification Current Progress Future Work

  3. Project Specification(Original) Perform further development on an existing Digilent Spartan-3 FPGA based application Perform a range of DSP, image and data processing functions.

  4. Project Specification(Updated) Export an existing Spartan 3 FPGA based application onto the Digilent Nexys Board Implement extra DSP functionality e.g. An FIR Filter

  5. System Overview

  6. Existing Hardware

  7. New Hardware - Nexys

  8. Graphical User Interface

  9. Current Work/Progress appliedVHDL course completed Reviewed Shane Agnew’s FYP Reviewed Antoin O’hAllmhurain’s FYP Downloaded counter program to Nexys board to prove functionality Nexys Board ready for CSR access Started implementing Nexys memory module in VHDL

  10. Future Work Implement new RAM BFM and Memory controller Implement current project with Nexys board – Completely functional Design an FIR filter in VHDL and Implement in the Project

  11. Questions?

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