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Digital Logic Structures

Digital Logic Structures. MOS transistors logic gates functional units of a computer. MOS: Metal-oxide Semiconductor. Basic electrical circuit: power supply, switch, lamp manipulating the switch makes/breaks the circuit. N-type: acts as a closed circuit when given a logically high voltage.

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Digital Logic Structures

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  1. Digital Logic Structures • MOS transistors • logic gates • functional units of a computer

  2. MOS: Metal-oxide Semiconductor • Basic electrical circuit: power supply, switch, lamp • manipulating the switch makes/breaks the circuit

  3. N-type: acts as a closed circuit when given a logically high voltage P-type: acts as a closed circuit when given a logically low voltage 2 Basic Types of Transistors gate gate Circuits with both are called CMOS

  4. Logic Gates • basic logic structures (AND, OR, NOT) are created out of CMOS transistors • inverter: recall the truth table for NOT in out out in

  5. OR and NOR gates • given the circuit, build the truth table • how do we get OR?

  6. AND and NAND gates • Construct NAND first, just as with NOR • NAND and NOR technology very widely used

  7. Notation for Digital Logic Gates • Inverter • AND, NAND • OR, NOR • a single bubble on an input or output denotes an inverter • multiple-input gates

  8. Expressions to Truth Tables NOT ((NOT A) or B) (A or B)

  9. Expressions to Truth Tables NOT ((NOT A) or B) (A or B)

  10. DeMorgan’s Laws • A AND B = A OR B • A OR B = A AND B

  11. Logic Structures • we build logic structures out of logic gates • logic structures are components of the microarchitecture of a computer • 2 kinds of logic structures • some store information • some do not store information

  12. Combinational Logic Structures • output is completely determined by the combination of input values • examples: • decoder • multiplexor (MUX) • full adder

  13. Decoder • outputs one 1 and the rest 0s where the 1 corresponds to a unique input pattern • for n inputs lines, 2n output lines • the output line that has the value 1 is asserted

  14. MUX • selects an input and connects it to the output • for 2n inputs lines, n select lines • MUX is represented by an upside down trapezoid

  15. 4 Input MUX

  16. Single Bit Adder a b ci co s 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1

  17. 4bit Adder

  18. Logical Completeness • we can build a circuit for any truth table using AND, OR, and NOT • proof by construction: • draw vertical lines for all inputs • for each 1 in the output value, connect 1s in the input directly to an AND gate (invert 0s); repeat for each row • OR all of the AND gates together

  19. Basic Storage Elements • R-S latch: simple structure that stores 1 bit of information • implemented with NAND gates • start with quiescent state (R=S=1) • as long as ‘a’ is 1, it stays 1 (same for 0) 1 1 1 0 0 1 1 1

  20. Reset/Set the Latch • put 0 on S while R=1, causes ‘a’ to become 1 • put 0 on R while S=1, causes ‘a’ to become 0 • behavior is undefined if both go to 0 10 1 0 1 0 10 1 1 1 quiescent

  21. The Gated D-latch • uses the R-S latch, plus some additional logic gates • D is the value that is stored, but it is only set/reset when WE (write-enable) is 1 • D’s value causes one of R or S to become 0 0 11 10 01 10 01

  22. Register • every computer offers a number of registers: high speed special memory locations • some registers have special meaning (e.g., PC is the program counter) • note that outputs in the 4-bit register are labeled by Q(n-1:0)

  23. Memory • memory location:collection of bits, has to be uniquely identified • identified by an address • the number of bits we have to represent addresses determines the maximum number of locations that can be accessed in memory 224 = 16,777,216 = 16MB locations

  24. Addressibility • the number of bits we have to represent the data gives the addressibility of the memory. E.g. The size of each memory location. • byte addressibility: convenient since characters are one byte • supercomputers may be 64-bit addressible for 64-bit floating point numbers

  25. 22 by 3 Memory Gated D-Latches 3-bit Value to be stored Address Decoding Logic 4 Rows 4 memory Locations • Trace how data is output and stored

  26. Preview of the LC-2 • memory • registers • Data (R0…R7, MDR, …) • Control (PC, MAR, ….) • multiplexers (MUXs) • Arithmetic Logic Unit (ALU) • Arithmetic operations (add, subtract) • Bitwise logical operations (or, and, ..)

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